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16.3.
MAIN
NO.3
(DSP/DPT
BLOCK)
2/4
1/4
4/4
3/4
(a)
(b)
(c)
(d)
(e)
(f)
(1)
(2) (3)
(4)
(5) (7)
(6)
(8)
KX-TVM50BX MAIN NO.3 (1/4)
D
C
B
A
4
6
5
3
2
1
RA824
10k
1
2
3
4
5
6
7
8
6
7
8
+3.3V
RA221
10k
4
1
2
36
7
8
5
+3.3V
33
R381
33
R384
R406
4.7K
RA823
10k
1
2
3
4
5
6
7
8
6
7
8
IC166
4
5
5
6
IC169
4
5
5
6
33 R382
IC166
1
2
2
3
RA220
10k
4
1
2
36
7
8
5
RA827
10k
1
2
3
4
5
6
7
8
6
7
8
IC169
1
2
2
3
+3.3V
33
R380
RA825
10k
1
2
3
4
5
6
7
8
6
7
8
+3.3V
33
R383
33
R386
RA828
22
1
2
3
4
5
6
7
8
6
7
8
IC133
#1G
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
2Y1
9
GND
10
2A1
11
1Y4
12
2A2
13
1Y3
14
2A3
15
1Y2
16
2A4
17
1Y1
18
#2G
19
VCC
20
TP718
RA830
22
1
2
3
4
5
6
7
8
6
7
8
C251
1.0u
L182
NC R388
+3.3V
C247
0.01u
C252
2.2u
DG
TP727
FIL128
1
2
3
C250
0.01u
DG
LD[5]
LD[4]
LD[3]
LD[2]
LD[7]
LD[1]
LD[6]
LD[0]
n_DSPCS[3]
HCNTL1
n_DSPCS[1]
HBIL
n_DSPINT[1]
n_DSPCS[2]
n_DSPRST[1]
n_DSPRST[3]
HCNTL0
DSP_RnW
n_DSPRST[2]
n_DSPINT[2]
n_DSPINT[3]
n_DSPINT[3]
n_ECO_CS[2]
n_ECO_RE
n_ECO_CS[3]
n_ECO_CS[1]
n_ECO_WE
n_RESET
n_ECO_GATE
n_DSP_GATE
RD_nWRG
IC166
12
13
13
11
n_ECO_INT
TP730
C266
2.2u
L184
C263
0.01u
DG
C264
1.0u
TP731
IC134
#1G
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
2Y1
9
GND
10
2A1
11
1Y4
12
2A2
13
1Y3
14
2A3
15
1Y2
16
2A4
17
1Y1
18
#2G
19
VCC
20
NC R390
C262
0.01u
FIL126
1
2
3
+3.3V
DG
DG
n_DSPHRDY
n_ECO_WAIT
IC166
10
9
9
8
33
R385
IC169
10
9
9
8
33
R387
IC201
5
A10
7
A11
8
A12
9
A13
10
A14
11
A15
99
D0
100
D1
101
D2
102
D3
103
D4
104
D5
105
113
D6
114
D7
115
D8
116
D9
117
D10
118
D11
119
D12
121
D13
122
D14
123
D15
131
A0
132
A1
133
A2
134 A3
136
A4
137
A5
138
A6
139
A7
140
A8
141
A9
DG
DG
LA[4]
LA[3]
LA[1]
LA[2]
LA[2]
LA[5]
LA[6]
LA[6]
LED800
R398
330
Q801
C295
0.01u
IC123
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
11
B8
12
B7
13
B6
14
B5
15
B4
16
B3
17
B2
18
B1
19
/2G
20
VCC
R768
33
RA835
22
1
2
4
3
6
5
7
8
5
7
8
RA836
22
1
2
3
4
5
6
7
8
6
7
8
33
R769
33
R770
33
R771
33
R772
33
R773
33
R774
33
R775
33
R776
n_ECO_WAIT12
DSPA_D[5]
DSPA_D[10]
DSPA_D[4]
n_DSP_RDY34
DSPA_D[13]
n_ECO_WAIT34
DSPA_D[11]
DSPA_D[15]
n_ECO_WAIT56
DSPA_D[0]
DSPA_D[12]
n_DSP_RDY56
n_DSP_RDY12
DSPA_D[1]
DSPA_D[9]
DSPA_D[3]
DSPA_D[8]
DSPA_D[14]
DSPA_D[2]
DSPA_D[6]
DSPA_D[7]
DSPA_D[7]
HDg[0]
HDg[1]
HDg[1]
HDg[6]
HDg[7]
HDg[7]
HDg[4]
HDg[3]
HDg[2]
HDg[5]
LD[7]
LD[6]
LD[5]
LD[4]
LD[3]
LD[2]
LD[1]
LD[0]
n_DSPINT[2]
n_DSPCS[1]
HCNTL0
n_DSPINT[1]
n_DSPRST[1]
n_DSPCS[2]
n_DSPRST[2]
n_DSPCS[3]
DSP_RnW
HCNTL1
HBIL
n_DSPINT[3]
n_DSPRST[3]
n_ECO_CS[2]
n_ECO_CS[1]
n_ECO_CS[3]
n_ECO_RE
n_RESET
n_ECO_INT
HCNTL0
n_ECO_RE
DSP_RnW
n_ECO_WE
HCNTL1
HBIL
HBIL
RD_nWRG
n_ECO_WE
LA[2]
LA[1]
LA[4]
LA[3]
LA[5]
LA[6]
LA[6]
OEP1
OSX
OSR
OSX
OSR
DPT_CLK
LAg[6]
LAg[1]
LAg[5]
LAg[3]
LAg[2]
LAg[4]
n_ECOREG
HBILG
n_ECOWEG
HCNTL0G
HCNTL1G
HCNTL1G
DSP_RWG
DG
A16
DSP HRDY Signal Control Circuit
ECO WAIT Signal Control Circuit
110
KX-
TVM5
0BX
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