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There can be as many as 12 on-board DSP´s. The interrupt signals from 12 DSP´s are sent to the HPI control interface of the
ASIC. Through this signal, an interrupt flag is asserted to the appropriate channel of the HPI interrupt register in the ASIC. At
the same time, an HPI interrupt signal notification is sent to the host CPU from the ASIC. The CPU which received the
notification of the HPI interrupt signal immediately reads the appropriate channel of the HPI interrupt register in the ASIC, clears
the register, and at the same time performs access to the DSP that sent the interrupt.
DSP
ASIC. Through this signal, an interrupt flag is asserted to the appropriate channel of the HPI interrupt register in the ASIC. At
the same time, an HPI interrupt signal notification is sent to the host CPU from the ASIC. The CPU which received the
notification of the HPI interrupt signal immediately reads the appropriate channel of the HPI interrupt register in the ASIC, clears
the register, and at the same time performs access to the DSP that sent the interrupt.
DSP
→
→
→
→ HOST CPU
When data or status changes that require signaling to the host occur, the HINT bit of the HPIC register above is asserted,
causing an assertion to the DSP chip´s /HINT external terminal. In concordance with this, the ASIC and host CPU perform
appropriate tasks such as reading designated registers of the DSP.
causing an assertion to the DSP chip´s /HINT external terminal. In concordance with this, the ASIC and host CPU perform
appropriate tasks such as reading designated registers of the DSP.
HOST CPU
→
→
→
→ DSP
When data transference becomes necessary from the host to the DSP, the CPU writes to the designated register, after
which DSPINT is asserted to the HPIC register, sending an interrupt to the DSP. In concordance with this interrupt, the DSP
performs appropriate task processing such as reading designated registers.
which DSPINT is asserted to the HPIC register, sending an interrupt to the DSP. In concordance with this interrupt, the DSP
performs appropriate task processing such as reading designated registers.
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•
•
• Reset
The DSP reset signal has individual reset signal capability, and performs system reset at POWER ON in addition to resets to
each DSP chip independently.
each DSP chip independently.
•
•
•
• Memory map
In addition to the internal on-chip memory, the DSP incorporates 32k-word high-speed external SRAM. The memory area that
can be accessed through the HPI-8 is 32KW of the on-chip RAM.
can be accessed through the HPI-8 is 32KW of the on-chip RAM.
•
•
•
• Concerning the LED on the DSP card
There is an LED mounted on the DSP card at the position shown in the diagram below. This LED is for servicing. When the DSP
downloads program software normally and moves into operating state, the DSP´s LED lights up. An unlit LED indicates
anomalies such as unsuccessful software downloads or failure of power supply to the DSP chip.
downloads program software normally and moves into operating state, the DSP´s LED lights up. An unlit LED indicates
anomalies such as unsuccessful software downloads or failure of power supply to the DSP chip.
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KX-TVM200BX
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