Read Panasonic KX-TDA6178X / KX-TDA6178XJ Service Manual online
6
KX-TDA6178X/KX-TDA6178XJ
5.2.
Circuit Operation
5.2.1.
Control-System Circuit
5.2.1.1.
CPU Peripherals
• CPU (System clock: 12.288 MHz)......IC601
Data bus: 16bit, Address bus: 23bit
• Flash ROM (512Kbyte)......IC602
Flash memory consists of two areas: boot space and administration space.
Administration program can be rewritten through downloading.
Administration program can be rewritten through downloading.
• SRAM (1Mbit)......IC603
Used for the data buffer for CPU work area, and SLT communication.
• Reset
Resets of an ECSLC24 card are roughly classified into the two kinds: ASIC reset and LPR reset.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
For approx. 1 second after LPR reset until the Config reset signal (Done pin) in FPGA is cancelled, access to FPGA is
restricted.First check configuration in FPGA is complete, then start accessing.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
For approx. 1 second after LPR reset until the Config reset signal (Done pin) in FPGA is cancelled, access to FPGA is
restricted.First check configuration in FPGA is complete, then start accessing.
Type of reset
Reset method
Specification
ASIC reset
ASIC reset is reset under the AND condition of reset signals (negative logic)
listed below.
listed below.
Power-on reset
Reset by reset IC
Hard reset from the main bus
Reset by EC_RST signal
Soft reset from the main bus
Released after the specified time
LPR reset
Soft reset from the main bus
Low active
Reset pulse width: 1.6 microseconds or more
Reset pulse width: 1.6 microseconds or more
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