Read Panasonic KX-TDA6105XJ / KX-TDA6105X Service Manual online
6 CIRCUIT OPERATIONS
5 BLOCK DIAGRAM
+3
.3
V
120pin Co
nne
cto
r CN702
nPRS_MEC
Bus Transceiver
IC101, IC102
D[0]-[31]
A[0],[17]-[25]
A[0],[17]-[25]
LD[0]-[15]
LA[1]-[16]
A[1]-[16]
CNT BUS
A
[2]-[15]
LA
[1
]-[16]
A
[17]-[21]
D[0]-[31]
LD
[0
]-[15]
DQM[0]-[3]
RD/
nW
R
nC
A
S
nR
A
S
nC
S3
CKE
C
K
IO_MEC
nCS_
SRAM[0]-[1]
DECODER
IC103
nCS4
nR
ESET
A
[21]-[25]
+3
.3
VB
nWE
,n
UB
,nLB
,nR
D
SRAM
4MB
IC107 IC108
+3
.3
V
B
SDRAM 16MB
IC105 IC106
+3
.3
V
MEC_MODE[0]-[3]
+3.3V
KX-TDA6105XJ/KX-TDA6105X BLOCK DIAGRAM
(No Mount)
6.1. EXPLANATION
The SRAM (IC107 and IC108) is mounted on the EMEC card.
These memories are controlled by the CPU (IC200) mounted on the EMPR.
These memories are controlled by the CPU (IC200) mounted on the EMPR.
7
KX-TDA6105XJ / KX-TDA6105X
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