Read Panasonic KX-TDA0156CE Service Manual online
47
KX-TDA0156CE
46 VCCINT
-
-
Core Supply Voltage
1.5V
47 GPIO15
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
48 TEST0
O
-
Not in use
Test purpose only
49 TEST1
O
Not in use
Test purpose only
50 TEST2
O
-
Not in use
Test purpose only
51 TEST3
O
-
Not in use
Test purpose only
52 HK_DET_O
O
-
Not in use
Test purpose only
53 NC53
O
-
RDI
RF RX data
54 NC54
-
Pull-up(Built in)
Not in use
-
55 NC55
-
Pull-up(Built in)
Not in use
-
56 NC56
I
-
RFSEL
RF control
57 NC57
I
-
RXDA_B
RF RX data
58 NC58
I
-
RXDA_A
RF RX data
59 NC59
O
-
SYEN_BL
RF control
60 NC60
O
-
SYEN_AL
RF control
61 NC61
I
-
SYSEL
RF control
62 NC62
I
-
LE
RF PLL control signal
63 GND
-
-
Digital ground
-
64 VCCINT
-
-
Core Supply Voltage
1.5V
65 GND
-
-
Digital ground
-
66 VCCIO
-
-
I/O Supply Voltage
3.2V
67 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
68 CD_PCMIN
I
Pull-up(Built in)
Not in use(open)
Test purpose only
69 CD_FSYNC
O
-
Not in use(open)
Test purpose only
70 CD_AUSEL
O
-
Not in use(open)
Test purpose only
71 CD_PCMOUT
O
-
Not in use(open)
Test purpose only
72 CD_PCMIN
O
-
Not in use(open)
Test purpose only
73 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
74 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
75 BER_CLK
O
-
Not in use
Test purpose only
76 PN9_ERR
O
-
Not in use
Test purpose only
77 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
78 NF0_O
O
-
Not in use(open)
-
79 NF0_I
I
-
DN_F0
8kHz Framehead from DNIC
80 GND
-
-
Digital ground
-
81 VCCIO
-
-
I/O Supply Voltage
3.2V
82 RIN_O
O
-
Not in use(open)
-
83 SIN_O
O
-
DN_DSTI
serial data to DNIC
84 SOUT_I
I
-
Not in use(pull up)
-
85 ROUT_I
I
-
DN_DSTO
serial data from DNIC
86 CONF_DONE
O
-
Configuration Conplete. to Reset Circuit
For FPGA Configuration
87 nSTATUS
I/O
-
Not in use(pull up)
For FPGA Configuration
88 TCK
I
-
Not in use(pull up)
for JTAG
89 TMS
I
-
Not in use(pull up)
for JTAG
90 TDO
O
-
Not in use
for JTAG
91 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
92 NC4M_I
I
-
DN_C4
Serial clock from DNIC
93 SCLK
I
-
System clock
16.384MHz
94 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
95 TDI
I
-
Not in use(pull up)
for JTAG
96 NC4M_O
O
-
Not in use(open)
-
97 CS3_N
O
-
Not in use(open)
Test purpose only
98 CS4_N
O
-
Not in use(open)
Test purpose only
99 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
100 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
101 GND
-
-
Digital ground
-
102 VCCIO
-
-
I/O Supply Voltage
3.2V
103 EC_DS
O
-
Not in use(open)
-
104 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
105 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
106 SF_FH
I
-
Superfame Select
0:FH, 1:SF
107 PSYNC
O
-
Superframe
1:Active
108 PCM_CLK
O
-
PCM_CK
2.048MHz
109 PCM_FSC0
O
-
PCM_F0
Framehead.8kHz
110 PCM_FSC1
O
-
PCM_F1
Frame pulse. 8kHz
111 PCM_DOUT
O
-
PCM_DN
output data to BBIC
112 PCM_DIN
I
-
PCM_UP
input data from BBIC
113 ACS2
I
-
FPGA Chip Select
0:Select
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