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52
KX-NS8290
11.5.5. PoE Circuit Waveform
11.5.6. Power & Reset Signal Waveform
11.5.7. NOR-Flash Memory Access Waveform
Description: PoE circuit FET gate control signal waveform
Ch1: FET_GATE(Q500-4)-PoE_G(T500-2)
Remark: Ground level is NOT DG
Ch1: FET_GATE(Q500-4)-PoE_G(T500-2)
Remark: Ground level is NOT DG
Description: PoE circuit FET drain voltage waveform
Ch1: FET_DRAIN(Q500-8)-PoE_G(T500-2)
Remark: Ground level is NOT DG
Ch1: FET_DRAIN(Q500-8)-PoE_G(T500-2)
Remark: Ground level is NOT DG
24
23
PWM control
interval
200 kHz
10V
PWM control
interval
200 kHz
88.7V
Description: Internal Voltage and Reset signal
Ch1: TP(RESET)-DG
Ch2: TP(+3.3V)-DG
Ch3: TP(+1.8V)-DG
Ch4: TP(+1.1V)-DG
Ch1: TP(RESET)-DG
Ch2: TP(+3.3V)-DG
Ch3: TP(+1.8V)-DG
Ch4: TP(+1.1V)-DG
[Power ON]
[Power OFF]
26
25
CH1: RESET
CH4:+1.1
CH3:+1.8
CH2:+3.3
Reset Pulse
56.9ms
56.9ms
Reset Detection
at 2.6V
at 2.6V
CH1: RESET
CH4:+1.1
CH3:+1.8
CH2:+3.3
Description: IC203 NOR Flash Memory Read Cycle Waveform
Ch1: A0(IC203-25) - DG
Ch2: #CE(IC203-26) - DG
Ch3: #OE(IC203-28) - DG
Ch4: DQ0(IC203-29) - DG
Ch1: A0(IC203-25) - DG
Ch2: #CE(IC203-26) - DG
Ch3: #OE(IC203-28) - DG
Ch4: DQ0(IC203-29) - DG
Description: IC203 NOR Flash Memory Write Cycle Waveform
Ch1: A0(IC203-25) - DG
Ch2: #CE(IC203-26) - DG
Ch3: #WE(IC203-11) - DG
Ch4: #DQ0(IC203-29) - DG
Ch1: A0(IC203-25) - DG
Ch2: #CE(IC203-26) - DG
Ch3: #WE(IC203-11) - DG
Ch4: #DQ0(IC203-29) - DG
28
27
CH1: A0
CH2: #CE
CH3: #OE
CH4: DQ0
Address Setup
62ns
62ns
Access Time
90ns
Read Cycle
294ns
CH1: A0
CH2: #CE
CH3: #WE
CH4: DQ0
Address Setup
90ns
90ns
Data Setup
60ns
60ns
Write Cycle
290ns
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