KX-NCP1290CJ (serv.man2) - Panasonic PBX Service Manual (repair manual). Page 6

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The CPU (IC1) is a single chip microcomputer of RISC architecture.
This item describes a memory interface (program & work) and peripheral functions.

Shows a list of the memory (program & work).

List of the memory (program & work) 

The CPU (IC1) has a chip select module as an internal peripheral and 8 chip select terminals are prepared outside. The area of
4Mbyte is assigned to a chip select terminal. (When DRAM is used, there is an exception partly, however it is not mentioned
here.)

Table of Chip Select Terminals

Table of Chip Select Port allocation

Part Name

Size

Purpose

Remarks

4M_Flash

4Mbit (256K x 16)

Program Area

Flash memory is employed for the software downloading by on-board.

4M_SRAM

4Mbit (256K x 16) 

Work Area

 

Terminals

Function used 

Wait Function 

(Numeral is no. of 

clocks.) 

Remarks 

CS Terminals

Individual Output 

(1)

Individual Output 

(2)

nCS0 (area 0)

-

-

nCS0

1+Programable 

or

1+Programable+WAIT
Terminals

Used for Flash memory CS.

nCS1 (area 1)

nCASH (DRAM)

-

nCS1

Read  1/Write  2  or
2+WAIT Terminals

Used for IC2 (ASIC) CS

nCS2 (area 2)

-

-

nCS2

1+Programable 

or

1+Programable+WAIT
Terminals

Used for SRAM CS. Work Area

nCS3 (area 3)

nCASL (DRAM)

-

nCS3

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS4 (area 4)

PA0 (I/O)

TIOCA0 (Timer)

nCS4

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS5 (area 5)

PA1 (I/O)

nRAS (DRAM)

nCS5

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS6 (area 6)

PA2 (I/O)

TIOCB0 (Timer)

nCS6

1+Programable 

or

1+Programable+WAIT
Terminals

Used for peripheral LSI CS.

nCS7 (area 7)

PA3 (I/O)

nWAIT

nWAIT

Read  1/Write  2  or
2+WAIT Terminals

Used for Input Wait Terminals.

Chip Select

Address

DeviceBit Wide

Assignment 

Device

Bus Cycle

Remarks

nCS0

0000000h
l
0FFFFFFh

16bit

4M_Flash

IC5

2 Clock (1+Long Wait1)

Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 2
(nCS2).

nCS1

1000000h
l
1FFFFFFh

8bit

ASIC

IC2

2+WAIT Terminals

Port allocation of byte by static bus sizing. 

nCS2

A000000h
l
AFFFFFFh

16bit

4M_SRAM

IC3

2 Clock (1+Long Wait1)

Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 0
(nCS0).

nCS6

6000000h
l
6FFFFFFh

8bit

PRI_IC

IC301

3 Clock (1+Long Wait2)

Port allocation of byte by static bus sizing.