KX-NCP1290CJ (serv.man2) - Panasonic PBX Service Manual (repair manual)

Model
KX-NCP1290CJ (serv.man2)
Pages
45
Size
1.68 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / PRI30 CARD
File
kx-ncp1290cj-sm2.pdf
Date

View Panasonic KX-NCP1290CJ (serv.man2) Service Manual online

ORDER NO. KMS0810582CE
PRI30 Card
Model No.
KX-NCP1290CJ
(for Asia, Oceania, Middle Near Esat, Africa and 
Latin America)
2
KX-NCP1290CJ
TABLE OF CONTENTS
PAGE
PAGE
1 Safety Precautions -----------------------------------------------3
1.1. For Service Technicians  ---------------------------------3
2 Warning --------------------------------------------------------------3
2.1. About Lead Free Solder (PbF: Pb free) --------------3
2.1.1. Suggested PbF Solder -------------------------------3
2.2. Discarding of P. C. Board --------------------------------4
3 Technical Descriptions------------------------------------------5
3.1. Block Diagram ----------------------------------------------5
3.2. Hardware Functional Specification --------------------6
3.2.1. CPU Peripheral Function ----------------------------6
3.2.2. ISDN Primary Rate Interface Function-----------8
3.2.3. Local Highway Interface Function-----------------9
3.2.4. EC Bus Interface ------------------------------------ 10
3.2.5. Outline of Reset System--------------------------- 11
3.2.6. Power Supply----------------------------------------- 12
4 Location of Controls and Components------------------ 13
4.1. Names and Locations----------------------------------- 13
5 Installation Instructions--------------------------------------- 14
5.1. Information about the Physical Trunk Cards ------ 14
5.1.1. PRI30 Card ------------------------------------------- 14
6 Troubleshooting Guide---------------------------------------- 16
6.1. PRI30-------------------------------------------------------- 16
7 Miscellaneous ---------------------------------------------------- 20
7.1. How To Replace a Flat Package IC ----------------- 20
7.1.1. Preparation-------------------------------------------- 20
7.1.2. Removal Procedure--------------------------------- 20
7.1.3. Procedure --------------------------------------------- 20
7.1.4. Removing Solder From Between Pins --------- 20
7.2. Terminal Guide of the ICs Transistors and
Diodes------------------------------------------------------- 21
8 Schematic Diagram--------------------------------------------- 22
8.1. No.1---------------------------------------------------------- 22
8.2. No.2---------------------------------------------------------- 24
8.3. No.3---------------------------------------------------------- 26
8.4. No.4---------------------------------------------------------- 28
8.5. No.5---------------------------------------------------------- 30
9 Printed Circuit Board ------------------------------------------ 31
9.1. Component View ----------------------------------------- 31
9.2. Bottom View ----------------------------------------------- 32
10 Appendix Information of Schematic Diagram --------- 33
11 Exploded View and Replacement Parts List ----------- 34
11.1. IC Data------------------------------------------------------ 34
11.1.1. IC1 (CPU) --------------------------------------------- 34
11.1.2. IC2 (ASIC)--------------------------------------------- 35
11.2. Mechanical Specification ------------------------------- 37
11.2.1. Table of Connectors -------------------------------- 37
11.3. Cabinet and Electrical Parts Location--------------- 39
11.4. Accessories and Packing Material------------------- 40
11.5. Replacement Parts List --------------------------------- 41
11.5.1. Cabinet and Electrical Parts Location ---------- 41
11.5.2. Accessories and Packing Materials------------- 41
11.5.3. Main Board Parts ------------------------------------ 41
3
     KX-NCP1290CJ
1 Safety Precautions
1.1.
For Service Technicians 
• Repair service shall be provided in accordance with repair technology information such as service manual so as to prevent fires,
injury or electric shock, which can be caused by improper repair work.
1. When repair services are provided, neither the products nor their parts or members shall be remodeled.
2. If a lead wire assembly is supplied as a repair part, the lead wire assembly shall be replaced.
3. FASTON terminals shall be plugged straight in and unplugged straight out.
• ICs and LSIs are vulnerable to static electricity.
When repairing, the following precautions will help prevent recurring malfunctions.
1. Cover plastic parts boxes with aluminum foil.
2. Ground the soldering irons.
3. Use a conductive mat on worktable.
4. Do not grasp IC or LSI pins with bare fingers.
2 Warning
2.1.
About Lead Free Solder (PbF: Pb free)
Note:
In the information below, Pb, the symbol for lead in the periodic table of elements, will refer to standard solder or solder that con-
tains lead.
We will use PbF when discussing the lead free solder used in our manufacturing process which is made from Tin, (Sn), Silver,
(Ag), and Copper, (Cu).
This model, and others like it, manufactured using lead free solder will have PbF stamped on the PCB. For service and repair
work we suggest using the same type of solder. 
Caution
• PbF solder has a melting point that is 50
° ~ 70° F, (30° ~ 40°C) higher than Pb solder. Please use a soldering iron with tempera-
ture control and adjust it to 700
° ± 20° F, (370° ± 10°C). 
Exercise care while using higher temperature soldering irons.:
Do not heat the PCB for too long time in order to prevent solder splash or damage to the PCB.
• PbF solder will tend to splash if it is heated much higher than its melting point, approximately 1100
°F, (600°C).
• When applying PbF solder to double layered boards, please check the component side for excess which may flow onto the
opposite side (See figure, below).
2.1.1.
Suggested PbF Solder
There are several types of PbF solder available commercially. While this product is manufactured using Tin, Silver, and Copper,
(Sn+Ag+Cu), you can also use Tin and Copper, (Sn+Cu), or Tin, Zinc, and Bismuth, (Sn+Zn+Bi). Please check the manufac
turer's specific instructions for the melting points of their products and any precautions for using their product with other 
materials. 
The following lead free (PbF) solder wire sizes are recommended for service of this product: 0.3mm, 0.6mm and 1.0mm.
4
KX-NCP1290CJ
2.2.
Discarding of P. C. Board
When discarding P. C. Board, delete all personal information such as telephone directory and caller list or scrap P. C. Board.
5
     KX-NCP1290CJ
3 Technical Descriptions
3.1.
Block Diagram
20MH
z
Line Interface Block
CLKOUT(4.096MHz or
 2.048MHz)
DSTi
DSTo
nF0b
nC4b
D[7:0]
A[4:0]
nIRQ
LOS
nRxMF
nTxMF
nRES
E1.5o/C1.5o
TX+
TX-
RX+
RX
-
DPLL IC302
f=12.288MHz
(CPU)
IC1
nIRQ1
nRES
nBREQ
nBACK
nWAIT
nIRQ0
PB[0]
nIRQ2
nIRQ3
nIRQ4
nIRQ5
PB[3]
RXD
TXD
PA[11]
PB[10]
Decode
r
(ASIC)
IC2
EC_CLK
EC_AD[15:0
]
EC_BE[1:0]
EC_FRAME
EC_TRDY
EC_STOP
EC_INT
EC_PART
EC_PERR
EC_nRST
EC_IDSEL
EC_DET
LDHW[1:0]
LUHW[1:0]
HW_FH
HW_CLK0
HW_CLK1
L_NETREF
SHW_FH
CT_NETREF
nCT_FRAME_
A
CT_CLK_A
CT_D[7:0]
TCK
TDI
TDO
TMS
TRST
P2[7]
nRESE
T
PLLCL
K
P0[7:0]
P1[3:0]
P2[0]
P2[1]
P2[6]
P3[0]
P3[4]
nCS_DMA
LD[7:0]
LA[12:0]
nRD
,nWR
nCSI
nCS[0]
nIRQ[1]
nIRQ[0]
P2[3]
P2[2]
nLRST
nBREQ
nBACK
nWAIT
+3.3V
J
u
mpe
r
Status
Indecation
 x
 5
Local
Reset
JTAG
RJ45
(C
O/EXT)
DHW0/DHW1(2.048Mbps)
UHW0/UHW1(2.048Mbps)
CLKOUT(4.096MHz or 2.048MHz)
nSHW_FH(8kHz)
nINT_ISD
DHW0
UHW0
nHW_FH(8kHz)
HW_CLK0(4M)
D7-0
A4-6
nRD,nWR
nCS_ISDN
nINT_ISDN
LOS
nRxMF
nTxMF
ISDN_RST
+3.3V
nREST
20MH
z
+3.3V
Flash
4Mbit
(256k x 16)
SRAM
4Mbit
(256k x 16)
+3.3
V
+
3.3V
+
3.3V
D15-0
A19-0
nRD
nWR
nLBS
nCS0
nCS1
nCS2
nCS3
nCS6
12.288M
z
nINT_ISDN
nINT_DSP
LOS
nRxMF
RYnBY
nCS_ISDN
nCS_DSP
+3.3
v
ISDN_RST
DSP_nRST
nTxMF
LOOPB
HRDY
nCS_DMA
D7-0
AIZ-0
nRD_nWR
nCS1
nINT_ISDN
nCS[0]_S
+3.3V
nRST
nHALT
EC_bus
28
H100 bus
11
CT
_
LO
OSC
16.384MHz
nRESET
RYnBY
nRESE
T
D15-0
A18-1
nWR,nRD
nCS0
D15-0
A18-1
nWR,nRD,nLBS,A0
nCS2
A10
nCS[0]_S
+15V
(PRI-
IC
)
IC301
Serge
EMC
Serge
EMC
Termination
Termination
Transforme
r
Transforme
r
Power
Thermisto
r
DC/DC
Converte
r
KX-NCP1290CJ BLOCK DIAGRAM
IC3
IC5
6
KX-NCP1290CJ
3.2.
Hardware Functional Specification
3.2.1.
CPU Peripheral Function
The CPU (IC1) is a single chip microcomputer of RISC architecture.
This item describes a memory interface (program & work) and peripheral functions.
3.2.1.1.
Memory (Program & Work)
Shows a list of the memory (program & work).
List of the memory (program & work) 
3.2.1.2.
Chip Select Logic
The CPU (IC1) has a chip select module as an internal peripheral and 8 chip select terminals are prepared outside. The area of
4Mbyte is assigned to a chip select terminal. (When DRAM is used, there is an exception partly, however it is not mentioned
here.)
Table of Chip Select Terminals
Table of Chip Select Port allocation
Part Name
Size
Purpose
Remarks
4M_Flash
4Mbit (256K x 16)
Program Area
Flash memory is employed for the software downloading by on-board.
4M_SRAM
4Mbit (256K x 16) 
Work Area
 
Terminals
Function used 
Wait Function 
(Numeral is no. of 
clocks.) 
Remarks 
CS Terminals
Individual Output 
(1)
Individual Output 
(2)
nCS0 (area 0)
-
-
nCS0
1+Programable 
or
1+Programable+WAIT
Terminals
Used for Flash memory CS.
nCS1 (area 1)
nCASH (DRAM)
-
nCS1
Read  1/Write  2  or
2+WAIT Terminals
Used for IC2 (ASIC) CS
nCS2 (area 2)
-
-
nCS2
1+Programable 
or
1+Programable+WAIT
Terminals
Used for SRAM CS. Work Area
nCS3 (area 3)
nCASL (DRAM)
-
nCS3
Read  1/Write  2  or
2+WAIT Terminals
CS Reserve
nCS4 (area 4)
PA0 (I/O)
TIOCA0 (Timer)
nCS4
Read  1/Write  2  or
2+WAIT Terminals
CS Reserve
nCS5 (area 5)
PA1 (I/O)
nRAS (DRAM)
nCS5
Read  1/Write  2  or
2+WAIT Terminals
CS Reserve
nCS6 (area 6)
PA2 (I/O)
TIOCB0 (Timer)
nCS6
1+Programable 
or
1+Programable+WAIT
Terminals
Used for peripheral LSI CS.
nCS7 (area 7)
PA3 (I/O)
nWAIT
nWAIT
Read  1/Write  2  or
2+WAIT Terminals
Used for Input Wait Terminals.
Chip Select
Address
DeviceBit Wide
Assignment 
Device
Bus Cycle
Remarks
nCS0
0000000h
l
0FFFFFFh
16bit
4M_Flash
IC5
2 Clock (1+Long Wait1)
Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 2
(nCS2).
nCS1
1000000h
l
1FFFFFFh
8bit
ASIC
IC2
2+WAIT Terminals
Port allocation of byte by static bus sizing. 
nCS2
A000000h
l
AFFFFFFh
16bit
4M_SRAM
IC3
2 Clock (1+Long Wait1)
Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 0
(nCS0).
nCS6
6000000h
l
6FFFFFFh
8bit
PRI_IC
IC301
3 Clock (1+Long Wait2)
Port allocation of byte by static bus sizing.
7
     KX-NCP1290CJ
3.2.1.3.
Interrupt
Shows the external interrupt image.
External interrupt image
Note:
• nHALT signal polls using I/O port to achieve the consistency with the existing PBX.
However, in case the CPU(IC1) moves to the sleep mode while the system is halted, the unit returns from the sleep mode receiv-
ing the interrupt signal in CPU(IC1) when nHALT is released in accordance with its specification. 
• The nIRQ[0] interrupt of ASIC(IC2) should be set to the output, which is used as an interrupt output to the CPU (IC1); mainly
DPRAM communication interrupt. 
The LOS signal of PRI-IC(IC301) is the level output which goes to "H" when the line reference is lost.
Consequently, inputting the inverted LOS signal to the CPU (IC1) enables to generate a negative edge interrupt while the line ref-
erence is lost.
Also setting nIRQ4 terminal of CPU(IC1) to I/O port makes polling possible.
The unit is provided with interrupt processing in order to achieve the consistency with the existing PBX.
Polling with I/O port is disable because nRxMF signal of PRI-IC(IC301) is generated in a periodical frame timing.
• The unit should be kept open with a jumper unpopulated to avoid conflicting between output of nIRQ[0] of ASIC(IC2) and the sig-
nal.
8
KX-NCP1290CJ
3.2.2.
ISDN Primary Rate Interface Function
3.2.2.1.
Line Interface Outline
The reference point of the line interface on the PRI30 card is Point S/T (Point U is not supported.) and the external and internal
line modes are supported as operating mode.
Also, the PRI23/PRI30 cards employ the PRI-IC (IC301) as the IC for Interface. See the "Line Interface Block" or the outline of
the interface connection. Shows the characteristics of the PRI-IC.
See the PRI-IC data sheet for detailed specifications.
Characteristics of the PRI-IC
3.2.2.2.
Line Interface Loopback
This card has a relay for loopback test on the primary side of the line to cut and divide into the line failure or the PBX's own fail-
ure, when there is a defect in operation.
Shows The outline diagram of the line interface loopback.
Outline diagram of the line interface
Item
Contents
Remarks
Line Extraction Clock
2.048MHz/PRI30
 
DPLL
Low Jitter DPLL for clk generation (IC302)
 
Elastic Buffer
Two-frame elastic buffer (Rx & Tx)
 
Signaling Controller
• HDLC Controller 
• CAS Controller
• Multiframe synchronization and synthesis ITU-T G.732 etc.
 
FIFO
64Byte x 2     128Byte x 3
 
PCM Highway Interface
2.048Mbps highway Interface
 
µP-Interface
8bit parallel Bus (Intel/Motorola)
Used Intel Mode for PRI30 Card.
9
     KX-NCP1290CJ
3.2.3.
Local Highway Interface Function
This card has the local highway at 2.048Mbps rate and local TSW in order to switch the talk channel (Bch), which is extracted
from ISDN primary rate by PRI-IC (IC301), to H.100 interface. (ASIC (IC2) internal module)
Also, the highway assignment is different for that the number of Bch differs in 2.048M system and 1.544M system. Shows the
highway timing.
For more information, see the ASIC (IC2) specification and PRI-IC (IC301) databook.
Highway timing
10
KX-NCP1290CJ
3.2.4.
EC Bus Interface
3.2.4.1.
Dual Port RAM (DPRAM) Communication
This card transmits and receives data between itself and MPR (EC bus) in a dual port RAM communication basically.
Shows the diagrammic illustration.
DPRAM Communication diagrammic illustration

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