KX-NCP1104XJ (serv.man2) - Panasonic PBX Service Manual (repair manual). Page 49

49

1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.

21

COL/RMII

Ipd/O

Mll Collision Detect Output. 
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping Options”
section for details.

22

CRS/RMll_BTB

Ipd/G

Mll Carrier Sense Output. 
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when RMII
mode is selected. See “Strapping Options” section for details.

23

GND

GND

Ground.

24 

VDDIO

P

Digital IO 2.5/3.3V tolerant power suppiy. 3.3V power input of voltage regulator. See “Circuit
Design Ref. for Power Supply” section for details.

25

INT#/PHYADO

Ipu/O

Management Interface (Mll) Interrupt Out. Interrupt level set by Register If, bit 9. 
During reset, latched as PHYAD[O]. See “Strapping Options” section for details.

26

LEDO/TEST

Ipu/O

Link/Activity LED Output. The external pull-down enable test mode and only used for the
factory test. Active low. 
Link/Act

Pin State

LED Definition    PHYADO

No Link

H

“Off”

Link

L

“On”

Act

-

“Toggle”

27

LED1/SPD-100/nFEF

Ipu/O

Speed LED Output Latched as SPEED (Register 0, bit 13) during power-up/reset. See
“Strapping Options” section for details. Active low.
Speed

Pin State

LED Definition

10BT

H

“Off”

100BT

L

“On”

28

LED2/

Ipu/O

Full-duplex LED Output Latched as DUPLEX (register Oh, bit 8) during power-up/reset. See
“Strapping DUPLEX Options” section for details. Active low.
Duplex

Pin State

LED Definition

Half

H

“Off”

Full

L

“On”

29

LED3/NWAYEN

Ipu/O

Collision LED Output. Latched as ANEG_EN (register Oh, bit 12) during power-up/reset See
“Strapping Options” section for details.
Collison

Pin State

LED Definition

No Collision

H

“Off”

Collision

L

“On”

30

PD#

Ipu

Power Down. 1 = Normal operation, 0 = Power-down. Active low.

31

VDDRX

P

Analog 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for details.

32

RX-

I    

Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.

33

RX+

I 

Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.

34

FXSD/FXEN

Ipd/O

Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The
default is “0”. See “100BT FX Mode” section for more details.

35

GND

GND

Ground.

36

GND

GND

Ground.

37

REXT

I

External resistor (6.49kW ) connects to REXT and GND.

38

VDDRCV

P

Analog 2.5V power supply. 2.5V power output of voltage regulator. See “Circuit Design Ref.
for Power Supply” section for details.

39

GND

GND

Ground.

40

TX-

O

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.

41

TX+

O

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.

42

VDDTX

P

Transmitter 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.

43

GND

GND

Ground.

44

GND

GND

Ground.

45

XO

O

XTAL feedback: Used with XI  for Xtal application.

46

XI

Crystal Oscillator Input: Input for a crystal or an external 25MHz clock. 
If ah oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no- connect .

47

VDDPLL

P

Analog PLL 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.

48

RST#

Ipu

Chip Reset. Active Ipw, minimum of 50

µs pulse is required.

Pin No.

Pin Name

I/O

Description