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48
KX-NCP1104XJ
12.1.2. IC4
Pin No.
Pin Name
I/O
Description
1
MDIO
I/O
Management Independent Interface (Mll) Data I/O. This pin requires an external 10K pull-up
resistor.
resistor.
2
MDC
I
MM Clock Input. This pin is synchronous to the MDIO.
3
RXD3/PHYAD
Ipd/O
Mll Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. When RXDV
is asserted, RXD [3..0] presents valid data to MAC through the Mll. RXD [3..0] is invalid
when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
is asserted, RXD [3..0] presents valid data to MAC through the Mll. RXD [3..0] is invalid
when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
4
RXD2/PHYAD2
Ipd/O
Mll Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
5
RXD1/PHYAD3
Ipd/O
Mll Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [3], See “Strapping
Options” section for details.
During reset, the pull-up/pull-down value is latched as PHYADDR [3], See “Strapping
Options” section for details.
6
RXDO/PHYAD4
Ipd/O
Mll Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See “Strapping
Options” section for details.
During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See “Strapping
Options” section for details.
7
VDDIO
P
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See “Circuit
Design Ref. for Power Supply” section for details.
Design Ref. for Power Supply” section for details.
8 GND
GND
Ground.
9
RXDV/CRSDV/PCS_LPBK
Ipd/O
Mll Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping Options”
section for details.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping Options”
section for details.
10
RXC
O
Mll Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
11
RXER/ISO
Ipd/O
Mll Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See “Strap-
ping Options” section for details.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See “Strap-
ping Options” section for details.
12 GND
GND
Ground.
13
VDDC
P
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply” section for
details.
details.
14
TXER
Ipd
Mll Transmit Error Input.
15
TXC/REFCLK
I/O
Mll Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock inter-
face, pull up XI to VDDPLL 2.5V via 10k
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock inter-
face, pull up XI to VDDPLL 2.5V via 10k
Ω resistor and leave XO pin unconnected.
16
TXEN
Ipd
Mll Transmit Enable Input.
17
TXDO
Ipd
Mll Transmit Data Input
18
TXD1
Ipd
Mll Transmit Data Input.
19
TXD2
Ipd
Mll Transmit Data Input
20
TXD3
Ipd
Mll Transmit Data Input.
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