KX-NCP1104XJ (serv.man2) - Panasonic PBX Service Manual (repair manual). Page 42

42

Total 

Signals

Interface 

Signals

Pin

GPIO, JTAG, Configuration, PLL, and 

Test Interface Signal Name

Signal 

Type

I/O Type

Signal Description

Pin Compatible & 

Enhanced Feature 

Modes

Software Selected 

Features

GPIO Interface

240

1

A1

GPIO0

Ihu/Ot16 General Purpose I/O 0. Internal pull-up. Pull-down option

and connection to a test point is recommended. Leave open
if not used.
Refer to M82xxx GPIO Usage App Note (82xxx-APP-010)
for information on GPIO allocation.

241

2

A2

GPIO1

I/O

Ihu/Ot16 General Purpose I/O 1. Same as GPIO0.

242

3

B3

GPIO2

I/O

Ihu/Ot16 General Purpose I/O 2. Same as GPIO0

243

4

C3

GPIO3

I/O

Ihu/Ot16 General Purpose I/O 3. Same as GPIO0

244

5

A4

GPIO4

I/O

Ihu/Ot16 General Purpose I/O 4. Same as GPIO0.

245

6

D3

GPIO5

I/O

Ihu/Ot16 General Purpose I/O 5. Same as GPIO0

246

7

C4

GPIO6

I/O

Ihu/Ot16 General Purpose I/O 6. Same as GPIO0

247

8

B4

GPIO7

I/O

Ihu/Ot16 General Purpose I/O 7. Same as GPIO0.

For Master Mode (i.e. Host is internal CSP ARM core) - MSP
Initialization. If standard code is used for the M825xx(2)
device, and it is operating with the CSP controlling the sys-
tem (no external host CPU), then GPIO7 will be dedicated to
supporting CSP re-start of the MSP, and will not be available
as an IO. In this case, leave open, no connect.
For Slave Mode (i.e. Host is an external uP Controller) - Boot
Loader Select. Selects the boot loader to use during power-
on reset initialization.
High = PCI/uP Parallel Bus Host Interface Mode Boot
Loader.
Low = Ethernet Interface Mode Boot Loader.

JTAG Interface

248

1

W3

TCK

I

Ihu

JTAG Test Clock. This is the JTAG clock signal. This pin has
an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.

249

2

Y4

TDI

I

Ihu

JTAG Test Input Data. This is the boundary scan serial input
signal, and it is shifted in on the rising edge of TCK. The pin
has an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.

250

3

Y3

TDO

O

Ots8

JTAG Test Output Data. This is the three-stateable boundary
scan data output signal, and it is shifted out on the falling
edge of TCK. It conforms to IEEE 1149.1 JTAG specification.

251

4

W1

TMS

I

Ihu

JTAG Test Mode Select. This is the control signal to the TAP
controller. This pin has an internal pull-up, and it conforms to
IEEE 1149.1 JTAG specification.

252

5

W5

TRST#

I

Ihu

JTAG Test Reset. A low signal forces the TAP controller into
a logic reset state. TRST# must be open (i.e., unconnected)
for normal (non-test) operation. This pin has an internal pull-
up, and it conforms to IEEE 1149.1 JTAG specification.

253

6

B1

JTAG_MODE

I

Ihu

JTAG Mode Select. Input with internal pull-up. To hold low,
connect to 100

Ω pull-down to GND.

Logic Low (0) = ARM only (for customer ICE)
Logic High (1) = ARM + SPU (for Mindspeed SPU debug)

Configuration, PLL, and Test Interface

254

1

U21

PLL_REFCLK

I

Ih

Reference Clock In. Connect to an external 10.000 MHz
clock.

255

2

U20

RESET#

I

Ih

Reset. Active low input asserted to initialize the M825xx(2)
device, including PCI-specific registers, sequencers, and
signals to a consistent reset state. Customers must imple-
ment a Host controllable method to activate the Hardware
Reset pin on each M825xx(2) device. This is required for all
M825xx(2) designs. The M825xx(2) Hardware Reset pin
must be held in the active (logic low) state for at least 2 ms,
for valid Reset operation. All clocks (REFCLK, PCI_CLK,
and TDM_CK) must be running for the M825xx(2) device to
perform a valid Reset operation.

256

3

C21

OPMODE1

I

Iu

Operation Mode 1. Used to select device configuration. Inter-
nal pull-up.

257

4

B22

OPMODE0

I

Iu

Operation Mode 0. Used to select device configuration. Inter-
nal pull-up.