KX-NCP1104XJ (serv.man2) - Panasonic PBX Service Manual (repair manual). Page 40

40

217

59

B12

PUI_CTRL1 SDR_DATA16 Reserved

I/O

I/
Opsts66

PUI_CTRL1: Master Mode Multifunction signal
(RLI_EMPTY_CLAV). In UTOPIA Master Mode, used as
RLI_EMPTY_CLAV signal.
Slave Mode Multifunction signal (TPI_ENB). In UTOPIA
Slave Mode, used as TPI_ENB signal.
SDR_DATA16: Same as SDR_DATA00.
Reserved. Leave open.

218

60

C12

PUI_CTRL2 SDR_DATA31 Reserved

I/O

I/
Opsts66

PUI_CTRL2: Master Mode Multifunction signal
(RLO_ENB). In UTOPIA Master Mode, used as
RLO_ENB signal.
Slave Mode Multifunction signal. Not used in UTOPIA
Slave Mode.
SDR_DATA31: Same as SDR_DATA00.
Reserved. Leave open.

219

61

A13

PUI_CTRL3 SDR_DATA17 Reserved

I/O

I/
Opsts66

PUI_CTRL3: Master Mode Multifunction signal. Not
used in UTOPIA Master Mode.
Slave Mode Multifunction signal (TPO_FULL_CLAV). In
UTOPIA Slave Mode, used as TPO_FULL_CLAV signal.
SDR_DATA17: Same as SDR_DATA00.
Reserved. Leave open.

Total 

Signals

Interface 

Signals

Pin

TDM Bus & Extra GPIO Interface 

Signal Name

Signal 

Type

I/O Type

Signal Description

Pin Compatible 

& Enhanced 

Feature Mode

S/W Selected 

Features

220

1

R2

TDM0_CK

TDM0_CK

I

I/
Opsts66

TDM Bus 0 Data Shift Clock. Shift clock input (1.544 MHz - 32.768
MHz) input from the T1/E1 Transceiver. Each TDM bus can be
connected to a different Frame Sync and Shift CLK.
Note: TDM0_CK must be provided when the TDM interface is
unused.

221

2

R1

TDM0_DR

TDM0_DR

I

I/
Opsts66

TDM Bus 0 Receive Data Input. Receive data input. A-Law/

µ-Law

PCM receive data sample from the T1/E1 Transceiver.

222

3

R3

TDM0_DX

TDM0_DX

O

I/
Opsts66

TDM Bus 0 Transmit Data Output. Tx data output. A-Law/

µ-Law

PCM transmit data sample to the T1/E1 Transceiver. Three-states
when not shifting. TDM_DX requires a 33

Ω series resistor, to

avoid problems caused by one driver turning off, while another
driver is turning on.

223

4

P4

TDM0_FS

TDM0_FS

I

I/
Opsts66

TDM Bus 0 Frame Sync. 8kHz frame sync input from the T1/E1
Transceiver. Each TDM bus can be connected to a different
Frame Sync and Shift CLK.
Note: TDM0_FS must be provided when the TDM interface is
unused.

224

5

P1

TDM1_CK

TDM1_CK

I

Ih

TDM Bus 1 Data Shift Clock. Shift clock input (1.544 MHz - 32.768
MHz) input from the T1/E1 Transceiver. Each TDM bus can be
connected to a different Frame Sync and Shift CLK.

225

6

P2

TDM1_DR

TDM1_DR

I

Ih

TDM Bus 1 Receive Data Input. Receive data input. A-Law/

µ-Law

PCM receive data sample from the T1/E1 Transceiver.

226

7

P3

TDM1_DX

TDM1_DX

O

I/
Opsts66

TDM Bus 1 Transmit Data Output. Tx data output. A-Law/

µ-Law

PCM transmit data sample to the T1/E1 Transceiver. Three-states
when not shifting. TDM_DX requires a 33

Ω series resistor, to

avoid problems caused by one driver turning off, while another
driver is turning on.

227

8

N4

TDM1_FS

TDM1_FS

I

Ih

TDM Bus 1 Frame Sync. 8kHz frame sync input from the T1/E1
Transceiver. Each TDM bus can be connected to a different
Frame Sync and Shift CLK.

228

9

N1

TDM2_CK

GPIO8

I/O

Ih/Ot16 TDM2_CK: TDM Bus 2 Data Shift Clock. Shift clock input (1.544

MHz - 32.768 MHz) input from the T1/E1 Transceiver. Each TDM
bus can be connected to a different Frame Sync and Shift CLK.
GPIO8: General Purpose I/O 8. Connect to pull-up if not used.

Total 

Signals

Interface 

Signals

Pin

Utopia & 2nd SDRAM Interface Signal 

Name

Signal 

Type

I/O Type

Signal Description

Pin 

Compatible 

Mode with 

Utopia Bus

Enhanced 

Feature Mode 

with Second 

SDRAM 

Interface

Enhanced 

Feature 

Mode with 

Extra GPIO