KX-HTS32RU, KX-HTS824RU - Panasonic PBX Service Manual (repair manual). Page 16

16

DSP Function

MIPS processor VPE1 thread
Dedicated Voice Firmware
Voice Codec PCM/G.711(u-law/A-law)/G.729a
Jitter buffer
Echo canceller
DTMF generate/receive

TDM side I/F

TDM clock slave mode
Interface signal
 FH_HW0 :   TDM Frame Header signal (8kHz from CPLD)
 UHW0 :       TDM Upstream Highway (to CPLD)
 DHW0 :       TDM Downstrem Highway (from CPLD)
 CLK_HW0 : TDM clock (4.096MHz from CPLD)

Power

For DSP operation, below voltage should be supplyed.
 3.3V   Internal PLL
 1.05V  CPU/DSP Core

Clock

DSP operation clock is generated by internal PLL device in CPU.

Reset

DSP reset signal is generated by internal reset login in CPU.

NFLASH_IO[1]
NFLASH_IO[0]

NFLASH_CLE_N

NFLASH_RE_N

NFLASH_CS1_N

NFLASH_ALE_N

NFLASH_RDBY_N

LED_D

LED_ST

LED_SH
CS_SPI
nRESET

DOUT
SCLK

UNITSEL1

UHW0

RWn

NFLASH_CS1_N

UNITSEL0
DEVSEL2
UNITSEL2

R151

R107

DG

R152

DEVSEL1

DEVSEL0

R137

R146

R153

FH_HW0

CLK_HW0

DHW0

R105

+3.3V_CPU

R128

R142

1

2

3

4

5

6

7

8

R127

R106

DIN

nWPS

R104

R136

R132

+3.3V_CPU

R129
R130
R131

nINT_PLD
USB_FLT0

R103

R111

8ms

R158

R147

1

2

3

45

6

7

8

R173

R148

R141

IC101

AB19

AB19

AC19

AC19

B1

B1

AC22

AC22

AB23

AB23

AB20

AB20

AC21

AC21

AB21

AB21

AC20

AC20

W20

W20

D15

D15

D12

D12

D9

D9

D10

D10

D11

D11

D8

D8

Y22

Y22

AA22

AA22

AA23

AA23

T20

T20

V20

V20

T19

T19

G23

G23

H22

H22

H23

H23

J23

J23

J22

J22

K22

K22

AB22

AB22

D14

D14

D13

D13

T23

T23

U19

U19

W22

W22

Y23

Y23

K23

K23

L22

L22

M22

M22

L23

L23

M23

M23

N22

N22

N23

N23

P23

P23

P22

P22

H20

H20

H19

H19

J20

J20

J19

J19

K19

K19

K20

K20

R125

1

2

7

8

R134

1

2

3

4

5

6

7

8

R135

(From CPLD)

(To CPLD)

(From CPLD)

(From CPLD)

(To CPLD)

(To CPLD)

(To CPLD)

(To CPLD)

(To CPLD)

(SLIC_INT)