Read Panasonic KX-FT57E Service Manual online
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KX-FT57E
Circuit Diagram
Timing Chart
about 175 ms
4.3
4.2
4.2
0.8
4.3
0.8
+5
about 175 ms
(2) When pin 3 of IC9 becomes low , it will prohibit the RAM (IC3) and Flash Memory (IC4) from changing data. The RAM (IC3)
will go into the backup mode, when it is backed up by a lithium battery.
(3) The watch dog timer which is built in the gate array (IC1), is initialized about every 1.5 ms.
When a watch dog error occurs, pin 104 of the gate array (IC1) becomes low.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
102
104
WDERR
101
IC1
R78
IC9
+5V
3
8
1
2
C64
C60
103
RESET
RESET
(TO ANALOG BOARD,
OPERATION BOARD)
OPERATION BOARD)
(TO MODEM)
3-2. RESET CIRCUIT
The output from pin 3 of the Reset IC (IC9) resets the gate array (IC1), the modem (IC5), the gate array on the operating board
(IC301), and the Port IC (IC5) on the analog board through IC1.
(IC301), and the Port IC (IC5) on the analog board through IC1.
(1) During momentary power failure, a positive reset pulse of 175 msec or more is generated and the system is completely
reset.
This is done to prevent partial resetting and system runaway during a power fluctuation.
This is done to prevent partial resetting and system runaway during a power fluctuation.
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