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8.2. VIDEO/AUDIO PROCESS BLOCK DIAGRAM
CCD
CCD SIGNAL
PROCESSOR
CCD CONTROL SECTION
U1
(CPU)
RGB0
RGB9
IC2
(SD CARD CONTROLLER)
DATA
ADDRESS
D15
D1
A15
A1
R1
P3
G1
7
8
9
1
2
5
10
12
DATA0
DATA1
DATA2
DATA3
CMD
CLK
C.DET
WP
HS1
(SD CARD CONNECTOR)
E15
SDDAT0
SDDAT3
D15
SDCMD
SDCLK
G15
SDWP
11
2
1
6
7
A10
DACOL
A9
DACOR
IC11
(HEADPHONE AMP)
VIN1
VIN2
VOUT1
VOUT2
1
3
4
5
6
2
JK1
(REMOCON)
LCD
FP1
17
FP1
16
FP1
15
FP1
14
FP1
13
FP1
12
FP1
11
FP1
10
FP1
9
FP1
8
FP1
7
FP1
6
U3
V3
W3
T4
U4
V4
V5
U5
T5
W7
V7
T8
LCD D2
LCD D3
LCD D4
LCD D5
LCD D6
LCD D7
LCD CLK
LCD HD
LCD VD
LCD SCK
LCD SDA
LCD SCS
CP1
2
CP1
1
LCD BACK LIGHT
AUDP1 G19
M1
(MICROPHONE)
5 CD
AUDP0 H16
CCD SIGNAL
FRONT-END
PROCESSOR
FRONT-END
PROCESSOR
N16 T19
DATA
BL H
V8 BL ON HI
D19 MICP
IC3
(SUB CPU)
MND0
F5
D3
DATA
MND15
G11
B7
MNA1
MNA15
ADDRESS
K8
J5
K2
M9
J9
L9
J12
B6
K12
L8
RDY
RDY MONI
WAKEUP
WAKEUP REQ
TX
RX
PWR STAT
NEW IF
CHG CNT
SD SELECT
B5
B4
U9
U8
B6
C6
V11
D2
D3
RDY MONI
RDY
WKUP
WKUP REQ
RXD
TXD
PWR STAT
REMO REQ
REMO SRS1
B17
SD SELECT
C15
H15
SDCD
4
IC4
(2CH MULTIPLEX)
COMMON
3
CH0
1
CH1
F15
D14
SDCLK536
6
A
J10
CHG BATT2
W12
AUD PSW
B19
AUD BEEP
L18
AUD MUTE
D21
L5
MUTE
D7
W15
AUD HPSEL
40
39
IC14
(6CH REGULATOR)
ON3
FB3L
4
IC10
(AUDIO AMP)
OUT
1 IN+
3
IN-
4
IC9
(AUDIO AMP)
OUT
1 IN+
BUZ1
(BUZZER)
(BUZZER)
VCC3R2AUD
D
S
G
Q7
(SIGNAL SELECT)
D
S
G
D
S
G
Q8
(MUTING)
Q9
(MUTING)
D
S
G
D
S
G
Q11
(MUTING)
Q10
(MUTING)
W17
OUTPUT MUTE
C2
REMOTE F17
P16
P19
R16
R19
E15 MICN
A15
B14
C14
D13
SDDAT0
SDDAT3
C17
A18
C13
SDCMDM
SDDET
SDWP
G2
G6
H2
H4
F4
F2
E2
E5
E9
E12
D12
D9
D8
E7
F12
F10
F9
F7
G10
R5
R8 R12
P12
D3
M2 M3 M13
N1
N3 N15
C3
H2
P4 P6
P8 P10 P11 P13
R4 R9 R10 R13
E14
D14
B18
EAR BEEP
SV-AS3PP/EB/EG/GC/GCS/GD/GN VIDEO/AUDIO PROCESS BLOCK DIAGRAM
VIDEO/AUDIO PROCESS BLOCK DIAGRAM
SV-AS3PP / SV-AS3EB / SV-AS3EG / SV-AS3GC / SV-AS3GCS / SV-AS3GD / SV-AS3GN
10
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