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8.3. CCD CONTROL/FLASH BLOCK DIAGRAM
U6
(CCD SIGNAL PROCESSOR)
52
47
D2
D11
IC201
Q201
IC1
(CCD IMAGE SENSOR)
VOUT
9
(CCD FRONT-END PROCESSOR)
L5
D0
(LSB)
OSUB
M3
XI
B10
P1
21
21
1
8
P1
15
15
P1
11
P1
4
P1
2
OV1
OV8
17
P1
13
13
P1
12
12
18
D9
(MSB)
Digital Main Signal (10 bit)
VDD
14
P1
16
16
SUBSW
X1
(49.0909MHz)
A10
XO
C12
HD
C13
VD
12
44
HD2 OUT
VD2 OUT
V1
ADC
CCD
VERTICAL
DRIVER
VERTICAL
DRIVER
VSUB
CCD
TIMING GENERATOR
TIMING GENERATOR
HL
B5
H1
H2
RG
NDF DRV0
V17
SHT DRV1
9
U7
(MOTOR DRIVE)
D1
V18
10
D2
CCD UNIT
U1
(CPU)
SERIAL
I/O
16 IO3
M
IRIS MOTOR
STRB CHG
T12
T16 STRB CHGRDY
T18 STRB TRIG
VDD
Q202
V6
16
P1
14
14
H2
HL
H1
S/H
S/H
CLAMP
CLAMP
15
11
B7
B4
E2
A7
SUBSW
R
DC
CONT.
CONT.
B9
A9
CLR
CLKO
16
15
21
22
DATA
5
4
7
33
34
40
39
42
61
62
DATA
RGB0
RGB9
DATA
14 HD IN
46 VD IN
30 RESETB
17 CLK IN
M10
CS
N11
DATA
M11
DCLK
U14
U15
T14
58
59
TIFSCK
TIFSDA
T
A
U13 TIF RES
31
W13
TIF SCS
TIF SCS
AFE TG SCS
AFE TG SDATA
AFE TG SCK
26
U19
CLK
ADCK
25
U18
THRU
TIF THROUGH
55
U17
PSAVE
TIF PWSAVE
P2
2,3
P2
1
P2
4
13 IO1
15 IO2
SHT DRV0
5
D0
V19
Q2
(CCD AMP)
Q3
(CCD AMP)
VCC12CCD
U16 SUB SW
J1
4
J1
6
J1
8
R16
R19
P16
P19
N16 T19
D2
D11
K11
K13
J13
J11
H11
G12
F13
G11
F11
N6
N8
N4
N10
L8 L12
M13
CCD CONTROL/FLASH BLOCK DIAGRAM
SV-AS3PP/EB/EG/GC/GCS/GD/GN CCD CONTROL/FLASH BLOCK DIAGRAM
TO FLASH
UNIT
UNIT
SV-AS3PP / SV-AS3EB / SV-AS3EG / SV-AS3GC / SV-AS3GCS / SV-AS3GD / SV-AS3GN
11
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