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7.3. SENSOR BLOCK DIAGRAM
IC3101
Q3101
1
IC3006
IC3004
IC3003
Q3002
IC3008
IC3001
IC3002
R
SUBSW
(CCD IMAGE SENSOR)
0H2
0H1
0V8
0V1
VO
VH
5
8
9
10
11
2
V2
V1
(V-CCD DRIVE)
3po
2po
INPUT
I/F
2po
3po
V4
V3
9
5
3
17
18
8
13
7
9
14
12
10
AD CLK
DS2
DS1
CPOB
PBLK
(TIMING PULSE GENERATOR)
TIMING
GENE
(CDS/AGC/AD)
30
19
20
21
22
16
CDS
AGC
(PGA)
SERIAL
I/F
A/D
(10bit)
(22.5MHZ)
48
47
46
D9(MSB)
D0(LSB) 2
44
38
39
46
47
9
10
11
S DATA
SCLK
CS
ST TRG
2FCK/4MHZ
STO
VD HEAD
HD HEAD
13
8
4
3
SUB
CH1
CH2
24
20
21
(V-CCD DRIVE)
3po
3po
2po
2po
5
3
17
18
7
9
14
12
8
13
CH3
CH4
22
23
(CLOCK GENERATOR)
FCK 2IN
6
1
X3001
(12MHZ)
3
4
H1A
H1B
H2A
H2B
34
28
31
25
(H-CCD DRIVE)
1
3
CCD3.1V
7
5
SUB UP LD
SUB
R
40
41
37
P3101
17
P3001
17
P3101
14
P3001
14
13
20
P3101
18
P3001
18
P3101
16
P3001
16
P3101
15
P3001
15
P3101
12
P3001
12
P3101
5
P3001
5
P3001
2
P3101
2
17
14
1,680pix
2,240pix
2,358pix
1,700pix
Ye
G
Ye
G
Cy
Mg
Cy
Mg
Cy
Mg
Cy
Mg
Ye
G
Ye
G
20
19
18
17
1688
1687
1686
1685
Ye
G
Ye
G
Cy
Mg
Cy
Mg
Cy
Mg
Cy
Mg
Ye
G
Ye
G
12
11
10
9
20
19
18
17
-COM CLK
11
1,680
2,240
16
16
78
8
8
2
2
8
OB
CCD Image Sensor (Unit: pixels)
: OB AREA
: TRANJENT AREA
: EFFECTIVE AREA
INPUT
I/F
V1
V4
CLKA
(45MHz)
XTAL IN
(12MHz)
(12MHz)
XTAL
OUT
SENSOR BLOCK DIAGRAM
DMC-LC5PP/E/B/A/EN SENSOR BLOCK DIAGRAM
IC6003-(280)
IC6003-(281)
IC6003
(ASIC)
(ASIC)
DMC-LC5PP / DMC-LC5E / DMC-LC5B / DMC-LC5A / DMC-LC5EN
11
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