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9.1. IC3001 DBE
Pin
No.
Signal Name
I/O
Description
1
AVSS1
-
GND
2
AVSS3
-
GND
3
AVSS4
-
GND
4
VCLK
I
27MHz Clock input terminal
5
VERT_RESE
T
T
-
Low:fixed
6
ZEB_SKIN
O
TEST port (TL3001)
7
USB_VDD
-
High:fixed (VDD)
8
RESET
I
Reset input terminal
9
SCAN
-
Low:fixed
10
TEST1/
GPI01
(RXD_T)
GPI01
(RXD_T)
I
USB differential amplifier input terminal
11
TEST4/
GPI04
(VPO)
GPI04
(VPO)
O
Differential driver signal output terminal
12
CD2
-
Low:fixed
13
CF_D11
-
High:fixed
14
CF_D13
-
High:fixed
15
CF_D7
-
High:fixed
16
CF_D15
-
High:fixed
17
N.C.
-
Not used
18
N.C.
-
Not used
19
N.C.
-
Not used
20
N.C.
-
Not used
21
N.C.
-
Not used
22
N.C.
-
Not used
23
N.C.
-
Not used
24
CF_WAIT
-
Low:fixed
25
CF_REG
-
Low:fixed
26
CF_D0
-
High:fixed
27
CF_D2
-
High:fixed
28
CF_D10
I
Data input terminal (fixed)
29
MD25
I
Data input terminal (fixed)
30
MD21
I
Data input terminal (fixed)
31
MD19
I/O
Data input/output terminal
32
MD30
I
Data input terminal (fixed)
33
MD16
I/O
Data input/output terminal
34
MA4
O
Address output terminal
35
MA3
O
Address output terminal
36
MA5
O
Address output terminal
37
MA1
O
Address output terminal
38
MA0
O
Address output terminal
39
MA9
O
Address output terminal
40
MA11
O
Address output terminal
41
MCLK_RET
(MCLK_I)
(MCLK_I)
I
Clock input
42
MCS[0]
(MCS)
(MCS)
O
Chip select output terminal
43
BSEL[0]
(Bank
Address 1)
(Bank
Address 1)
O
Bank address output terminal
44
RAS
(Raw
Address
Strobe)
(Raw
Address
Strobe)
O
Bertical address latch trigger
input terminal
(Low:Active)
input terminal
(Low:Active)
45
DQM0
(DQML)
(DQML)
I/O
Input maskable/Output enable
46
MD9
I/O
Data input/output terminal
47
MD5
I/O
Data input/output terminal
48
MD12
I/O
Data input/output terminal
49
MD2
I/O
Data input/output terminal
50
MD15
I/O
Data input/output terminal
51
CPUSEL[1]
-
Low:fixed
Pin
No.
Signal Name
I/O
Description
52
SA0
O
Address output terminal
53
SA2
O
Address output terminal
54
SA5
O
Address output terminal
55
SA8
O
Address output terminal
56
SA12
O
Address output terminal
57
SA15
O
Address output terminal
58
RD
I
Output(read) enable input terminal
59
WRH
I
WRH input terminal
60
CS
I
Chip select input terminal
61
SD14
I/O
Data input/output terminal
62
SD11
I/O
Data input/output terminal
63
SD7
I/O
Data input/output terminal
64
SD4
I/O
Data input/output terminal
65
SD0
I/O
Data input/output terminal
66
AFE_D10
I/O
Data input/output terminal
67
AFE_D6
I/O
Data input/output terminal
68
AFE_D2
I/O
Data input/output terminal
69
AFE_CLK3X
I
Clock input
70
AFE_VPIX
I
VPIX input terminal
71
SER_SDEN
-
High:fixed
72
SER_SD
-
High:fixed
73
COMP+
I
Comparator +signal input terminal
74
Cr+(R)
O
Cr signal output terminal
75
CORE_VSS
-
GND
76
CARRIER_O
-
Low:fixed
77
HSYNC
I
HSYNC input terminal
78
USB_D+
I/O
USB input/output (+) terminal
79
USB_4XCLK
I
48MHz clock input terminal
80
TME
-
Low:fixed
81
TEST2/
GPI02
(VP)
GPI02
(VP)
I
Output gate control signal input
terminal
(with VM)
terminal
(with VM)
82
TEST5/
GPI05
(VMO)
GPI05
(VMO)
O
Differential driver signal output terminal
83
CD1
-
Low:fixed
84
CF_D4
-
High:fixed
85
CF_D6
-
High:fixed
86
N.C.
-
Not used
87
N.C.
-
Not used
88
N.C.
-
Not used
89
N.C.
-
Not used
90
CF_RDY
-
Low:fixed
91
VDD
-
VDD
92
N.C.
-
Not used
93
N.C.
-
Not used
94
N.C.
-
Not used
95
BVD1
-
Low:fixed
96
CF_D9
-
High:fixed
97
N.C.
-
Not used
98
MD22
I
Data input terminal (fixed)
99
MD27
I
Data input terminal (fixed)
100
MD29
I/O
Data input/output terminal
101
MD17
I
Data input terminal (fixed)
102
VSS
-
GND
103
VDD
-
VDD
104
MA2
O
Address output terminal
105
MA7
O
Address output terminal
106
MA8
O
Address output terminal
107
BA1
(Bank
Address 1)
(Bank
Address 1)
O
Bank address output terminal
108
CORE_VSS_
PLL
PLL
-
GND
109
RT_MCLKIN
-
Low:fixed
9 I/O CHART
23
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
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