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8.4. SENSOR BLOCK DIAGRAM
IC3101
Q3101
X3001
IC3003
Q3002
IC3002
R
(CCD IMAGE SENSOR)
V6
V1
VO
8
12
9
V2
V1
(V-CCD DRIVE)
3po
2po
INPUT
I/F
2po
3po
V4
V3
12
16
9
5
15
24
28
23
27
1
25
26
(CDS/AGC/AD/TIMING PULSE GENERATOR)
43
CDS
AGC
(PGA)
A/D
(12bit)
D2
D0
(LSB)
62
51
50
49
SDATA
SCLK
CS
ST TRG
STROBE
VD
HD
53
57
60
SUBCLK
V5(CH1)
V6(CH2)
13
18
19
20
2
V7(CH3)
V8(CH4)
20
23
(CLOCK GENERATOR)
CLI 36
3
4
2
H1
H2
26
27
V SUB
R
12
33
FP9008
2
2
6
FP9002
1
FP9002
7
FP9002
12
FP9002
15
17
14
1536pix
2048pix
2140pix
1561pix
B
Gr
B
Gr
Gb
R
Gb
R
Gb
R
Gb
R
B
Gr
B
Gb
12
11
10
9
1230
1229
1228
1227
B
Gr
B
Gr
Gb
R
Gb
R
Gb
R
Gb
R
B
Gr
B
Gr
10
9
8
7
12
11
10
9
64
1536
2048
20
20
48
7
4
2
9
7
OB
CCD Image Sensor (Unit: pixels)
: OB AREA
: TRANJENT AREA
: EFFECTIVE AREA
V1
V4
CLK
(24.75MHz)
XTAL IN
(12MHz
(12MHz
XTAL
OUT
3po
2po
17
4
V5
V7
SUB
15
FP9002
4
FP9002
3
16
CH1
CH2
To IC6005
CCDVD
CCDHD
D11
(MSB)
D3
1
9
Digital Main Signal
3.1V
VH
To IC6005
SENSOR BLOCK DIAGRAM
DMC-F1PP/PM/E/B/A/EN/T/KR SENSOR BLOCK DIAGRAM
DMC-F1PP / DMC-F1PM / DMC-F1E / DMC-F1B / DMC-F1A / DMC-F1EN / DMC-F1T / DMC-F1KR
16
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