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8 SCHEMATIC DIAGRAMS
8.1. POWER BLOCK DIAGRAM
D
S
G
D3.1V
Q1011
F1001
Q1001
13
JK1001
37
45
39
38
CH1
PULSE
SHAPER
IC1001
(6CH SW REGULATOR IC)
TRIANGLE
OSC
13
2
3
OUT1
IN-1
EQ1
FP9008
10
FP9008
6
IC6005
(VENUS)
2
4
3
46
BATTERY
TERMINAL
TERMINAL
ON
OFF
POWER SW
TOP OPERATION SW
SW3.1V
SW3.1V
QR9102
QR9106
QR1006
13
POW
L
POFF
L
Q1002
14
POFF
H
14
16
LCD ON
H
CCD ON
H
D9103
C9108
Vref
Q1004
CH2
PULSE
SHAPER
16
4
6
OUT2
IN-2
EQ2
Vref
CH3
PULSE
SHAPER
18
8
9
OUT3
IN-3
EQ3
Vref
CH4
PULSE
SHAPER
19
33
35
OUT4
FB4
EQ4
Vref
CH5
PULSE
SHAPER
21
31
30
OUT5
FB5
EQ5
Vref
CH6
PULSE
SHAPER
23
29
27
OUT6
FB6
EQ6
Vref
0.9V
Vref
Vref
R
Q
S
Vref
14
44
43
42
CTL5
CTL6
V BAT
L
off
CTL2
CTL1
CTL3,4
5V
D
S
G
AF3.4V
Q1012
7
FB3
D
S
G
D1.5V
Q1010
34
IN-4
D
S
G
T1002
4
3
6
5
1
7
8
BL12V
LCD8.5V
D
S
G
T1001
4
3
6
5
1
7
8
CCD12V
CCD-8V
Q1009
Q1008
UNREG
1
2
D
S
G
5
Q1006
Q1007
POWER BLOCK DIAGRAM
DMC-F1PP/PM/E/B/A/EN/T/KR POWER BLOCK DIAGRAM
DMC-F1PP / DMC-F1PM / DMC-F1E / DMC-F1B / DMC-F1A / DMC-F1EN / DMC-F1T / DMC-F1KR
13
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