Read LG 50PX950-UA / 50PX950-UF (CHASSIS:PU02B) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R120
100
RA2-
C102
0.1uF
50V
0.1uF
50V
R122
100
RD1+
RCLK1-
RD2+
RB1-
/3D_FPGA_RESET
RC2+
R111
100
RA2+
R113
100
RE1-
RCLK1+
R103
0
C101
10uF
16V
10uF
16V
RE2-
R115
100
RB1+
RCLK2-
R117
100
RB2-
R119
100
R121
100
RE1+
RE2+
RC1-
RCLK2+
RA1-
RB2+
R112
100
R114
100
RD1-
RC1+
RD2-
R116
100
C103
100pF
50V
100pF
50V
RA1+
RC2-
R118
100
+5V
PC_SER_CLK
R101
0
R102
0
R104
0
PC_SER_DATA
SCL3_3.3V
R105
0
R106
0
R107
0
DISP_EN
SDA3_3.3V
MOD_ROM_TX
MOD_ROM_RX
R108
0
3D_SYNC_OUT
R123
0
R124
0
TCK
TDI
P104
YFDW254-10S
1
2
3
4
5
6
7
8
9
10
2V5
R130
22
R128
1K
R125
22
C125
0.1uF
16V
R126
1K
TMS
R129
1K
R127
22
TDO
R131
22
TB2-
TA2+
TD3+
TC3+
TA4-
TD4-
TB1+
TB4+
TCLK4-
TCLK4+
TCLK2-
TB3+
TB1-
TE2+
TE2-
TD1-
TA1+
TB3-
TC3-
TB2+
TD2-
TD4+
TC1+
TCLK3-
TE3-
TCLK3+
TA4+
TC4-
TD2+
TD1+
TE4+
TE3+
TCLK2+
TE1-
TA2-
TC4+
TA1-
TC2+
TE1+
TA3-
TE4-
TD3-
TCLK1+
TA3+
TCLK1-
TB4-
TC2-
TC1-
PC_SER_CLK
PC_SER_DATA
DISP_EN
R850
0
R849
4.7K
2N7002(F)
Q800
G
D
S
R846
4.7K
2N7002(F)
Q801
G
D
S
R851
4.7K
R847
0
R848
4.7K
SDA3_3.3V
SCL3_3.3V
TRE2-
C901
0.1uF
16V
0.1uF
16V
TCLK3-
TE2+
MSEL[3]
TB1+
TE4-
TRB2-
DATA0
TC3+
TRA2-
TC2+
TCLK1+
TA1+
TCLK2+
/CE
TRCLK2-
SCL3_3.3V
TMS
TB3-
TB3+
1V2
TD4+
TRD2+
TA2-
TC4+
TRE2+
1V2
1V2
SDA3_3.3V
TD3-
TRD2-
TCLK1-
TRE1-
TDO
TD4-
TRB1+
TC1+
TB2+
2V5
TE1-
TRD1-
TB4+
TE3+
TCK
TA1-
C902
0.1uF
16V
0.1uF
16V
TB4-
TCLK4+
TRA1-
TB2-
TA3-
TD3+
TB1-
TRA1+
TC2-
TRB1-
MSEL[2]
TDI
TRC1+
R4059
0
READY
TE4+
CONFIG_DONE
TC4-
2V5
2V5
1V2
TRCLK1-
TCLK4-
DCLK
TRA2+
TRD1+
TCLK2-
C904
0.1uF
16V
0.1uF
16V
/STATUS
C905
0.1uF
16V
0.1uF
16V
TRCLK2+
C908
0.1uF
16V
0.1uF
16V
TD1+
TA4+
TA3+
C906
0.1uF
16V
TA2+
TC1-
TRC2-
ASDO
MSEL[0]
TRC1-
TE3-
TD2-
2V5
SYSCLK
TCLK3+
TC3-
TE1+
TD1-
TRE1+
C907
0.1uF
16V
0.1uF
16V
MSEL[1]
C903
0.1uF
16V
0.1uF
16V
/CONFIG
/3D_FPGA_RESET
TE2-
TRC2+
/CSO
TD2+
TRB2+
TRCLK1+
TA4-
3D_SYNC_OUT
X901
54.0000MHz
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
R944
10K
R949
22
22
C909
0.1uF
16V
0.1uF
16V
SYSCLK
R950
10K
10K
/STATUS
R951
10K
10K
2V5
/CE
CONFIG_DONE
R952
10K
10K
R953
1K
1K
/CONFIG
DCLK
R964
22
22
L902
BLM18PG121SN1D
C920
100pF
50V
100pF
50V
C919
0.1uF
16V
0.1uF
16V
R968
22
22
ASDO
/CSO
C917
10uF
16V
10uF
16V
R967
22
22
IC904
EPCS16SI8N_
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
C921
10pF
10pF
DATA0
2V5
R965
27
27
AR901
22
1/16W
2V5
R987
0
OPT
R982
0
OPT
R988
0
MSEL[3]
MSEL[0]
MSEL[2]
MSEL[1]
R984
0
OPT
3V3
3V3
L/R_DETECT
MOD_ROM_TX
MOD_ROM_RX
R704
0
R705
0
R702
0
R703
0
R701
0
R700
0
L/R_DETECT
3V3
R4060
22
22
R4061
22
22
R4062
22
22
R4063
22
22
P101
FI-R51S-HF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
R141
100
R142
100
R143
100
R144
100
R145
100
R146
100
R147
100
R148
100
R149
100
R150
100
R151
100
R152
100
P2001
104060-8017
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
3D_SYNC_OUT
E_TDI
E_TMS
E_TDO
E_TCK
R161
22
TCK_FLASH
E_TCK
R159
2K
Q151
FDV301N
G
D
S
R160
4.7K
2V5
R158
5.6K
OPT
R157
0
R162
0
Q152
FDV301N
G
D
S
R163
5.6K
OPT
R166
22
2V5
TDO_FLASH
E_TDO
R164
2K
R165
4.7K
R169
2K
Q153
FDV301N
G
D
S
R168
5.6K
OPT
TMS_FLASH
2V5
E_TMS
R167
0
R171
22
R170
4.7K
R172
0
R174
2K
R176
22
Q154
FDV301N
G
D
S
2V5
R175
4.7K
E_TDI
R173
5.6K
OPT
TDI_FLASH
3V3
3V3
3V3
3V3
R986
0
R983
0
R985
0
R989
0
OPT
3V3
L151
BLM18PG121SN1D
OPT
R153
0
0
TMS_FLASH
R154
0
0
TDI_FLASH
R155
0
0
TCK_FLASH
R156
0
0
TDO_FLASH
FPGA_D/L
2V5
R181
4.7K
FPGA_D/L
R178
10K
R179
10K
R182
22
22
Q156
2SC3052
2SC3052
E
B
C
R180
10K
Q155
2SC3052
2SC3052
E
B
C
R183
0
R185
4.7K
R184
10K
2V5
/CE
Q157
2SC3052
2SC3052
E
B
C
R186
22
/CONFIG
3V3
IC1000
EP3C55F484C6N_SHRINK
A11
B8_IO[0]
B11
B8_IO[1]
D10
B8_IO[2]
E10
B8_IO[3]
A10
B8_IO[4]
B10
B8_IO[5]
A9
B8_IO[6]
B9
B8_IO[7]
C10
B8_IO[8]
G11
B8_IO[9]
A8
B8_IO[10]
B8
B8_IO[11]
A7
B8_IO[12]
B7
B8_IO[13]
A6
B8_IO[14]
B6
B8_IO[15]
E9
B8_IO[16]
C8
B8_IO[17]
C7
B8_IO[18]
D8
B8_IO[19]
E8
B8_IO[20]
A5
B8_IO[21]
B5
B8_IO[22]
G10
B8_IO[23]
F10
B8_IO[24]
C6
B8_IO[25]
D7
B8_IO[26]
A4
B8_IO[27]
B4
B8_IO[28]
F8
B8_IO[29]
G8
B8_IO[30]
A3
B8_IO[31]
B3
B8_IO[32]
D6
B8_IO[33]
E7
B8_IO[34]
C3
B8_IO[35]
C4
B8_IO[36]
F7
B8_IO[38]
G7
B8_IO[39]
F9
B8_IO[40]
E6
B8_IO[41]
E5
B8_IO[42]
G9
B8_IO[43]
IC1000
EP3C55F484C6N_SHRINK
F6
VCCD_PLL3
F5
GNDA3
G6
VCCA3
G4
B1_IO[0]
G3
B1_IO[1]
B2
B1_IO[2]
B1
B1_IO[3]
G5
B1_IO[4]
E4
B1_IO[5]
E3
B1_IO[6]
C2
B1_IO[7]
C1
B1_IO[8]
D2
B1_IO[9]
D1
B1_IO[10]
H7
B1_IO[11]
H6
B1_IO[12]
J6
B1_IO[13]
H4
B1_IO[14]
H3
B1_IO[15]
E2
B1_IO[16]
E1
B1_IO[17]
F2
B1_IO[18]
F1
B1_IO[19]
J5
B1_IO[20]
H5
B1_IO[21]
K6
nSTATUS
J7
B1_IO[22]
K7
B1_IO[23]
J4
B1_IO[24]
H2
B1_IO[25]
H1
B1_IO[26]
J3
B1_IO[27]
J2
B1_IO[28]
J1
B1_IO[29]
K2
DCLK
K1
B1_IO[30]
K5
nCONFIG
L5
TDI
L2
TCK
L1
TMS
L4
TDO
L3
nCE
G2
CLK0
G1
CLK1
IC1000
EP3C55F484C6N_SHRINK
T2
CLK2
T1
CLK3
L6
B2_IO[0]
M6
B2_IO[1]
M2
B2_IO[2]
M1
B2_IO[3]
M4
B2_IO[4]
M3
B2_IO[5]
N2
B2_IO[6]
N1
B2_IO[7]
M5
B2_IO[8]
P2
B2_IO[9]
P1
B2_IO[10]
R2
B2_IO[11]
R1
B2_IO[12]
N5
B2_IO[13]
P4
B2_IO[14]
P3
B2_IO[15]
U2
B2_IO[16]
U1
B2_IO[17]
V2
B2_IO[18]
V1
B2_IO[19]
P5
B2_IO[20]
N6
B2_IO[21]
R4
B2_IO[22]
R3
B2_IO[23]
W2
B2_IO[24]
W1
B2_IO[25]
Y2
B2_IO[26]
Y1
B2_IO[27]
T3
B2_IO[28]
N7
B2_IO[29]
P7
B2_IO[30]
AA2
B2_IO[31]
AA1
B2_IO[32]
V4
B2_IO[33]
V3
B2_IO[34]
P6
B2_IO[35]
R5
B2_IO[36]
T4
B2_IO[37]
T5
B2_IO[38]
R6
B2_IO[39]
T6
VCCA1
U5
GNDA1
U6
VCCD_PLL1
IC1000
EP3C55F484C6N_SHRINK
F16
B7_IO[0]
E16
B7_IO[1]
F15
B7_IO[2]
G16
B7_IO[3]
G15
B7_IO[4]
F14
B7_IO[5]
C18
B7_IO[6]
D18
B7_IO[7]
D17
B7_IO[8]
C19
B7_IO[9]
D19
B7_IO[10]
A20
B7_IO[11]
B20
B7_IO[12]
C17
B7_IO[13]
B19
B7_IO[14]
A19
B7_IO[15]
A18
B7_IO[16]
B18
B7_IO[17]
D15
B7_IO[18]
E15
B7_IO[19]
G14
B7_IO[20]
G13
B7_IO[21]
A17
B7_IO[22]
B17
B7_IO[23]
A16
B7_IO[24]
B16
B7_IO[25]
C15
B7_IO[26]
E14
B7_IO[27]
F13
B7_IO[28]
A15
B7_IO[29]
B15
B7_IO[30]
C13
B7_IO[31]
D13
B7_IO[32]
E13
B7_IO[33]
A14
B7_IO[34]
B14
B7_IO[35]
A13
B7_IO[36]
B13
B7_IO[37]
E12
B7_IO[38]
E11
B7_IO[39]
F11
B7_IO[40]
A12
CLK8
B12
CLK9
IC1000
EP3C55F484C6N_SHRINK
G22
CLK5
G21
CLK4
M18
CONF_DONE
M17
MSEL0
L18
MSEL1
L17
MSEL2
K20
MSEL3
L22
B6_IO[0]
L21
B6_IO[1]
K19
B6_IO[2]
K22
B6_IO[3]
K21
B6_IO[4]
J22
B6_IO[5]
J21
B6_IO[6]
H22
B6_IO[7]
H21
B6_IO[8]
K17
B6_IO[9]
K18
B6_IO[10]
J18
B6_IO[11]
F22
B6_IO[12]
F21
B6_IO[13]
J20
B6_IO[14]
J19
B6_IO[15]
J17
B6_IO[16]
H20
B6_IO[17]
H19
B6_IO[18]
E22
B6_IO[19]
E21
B6_IO[20]
H18
B6_IO[21]
H16
B6_IO[22]
D22
B6_IO[23]
D21
B6_IO[24]
F20
B6_IO[25]
F19
B6_IO[26]
G18
B6_IO[27]
H17
B6_IO[28]
C22
B6_IO[29]
C21
B6_IO[30]
B22
B6_IO[31]
B21
B6_IO[32]
C20
B6_IO[33]
D20
B6_IO[34]
F17
B6_IO[35]
G17
B6_IO[36]
F18
VCCA2
E18
GNDA2
E17
VCCD_PLL2
IC1000
EP3C55F484C6N_SHRINK
V17
VCCD_PLL4
V18
GNDA4
U18
VCCA4
AA22
B5_IO[0]
AA21
B5_IO[1]
T17
B5_IO[2]
T18
B5_IO[3]
W20
B5_IO[4]
W19
B5_IO[5]
Y22
B5_IO[6]
Y21
B5_IO[7]
U20
B5_IO[8]
U19
B5_IO[9]
W22
B5_IO[10]
W21
B5_IO[11]
T20
B5_IO[12]
T19
B5_IO[13]
R17
B5_IO[14]
P17
B5_IO[15]
V22
B5_IO[16]
V21
B5_IO[17]
R20
B5_IO[18]
U22
B5_IO[19]
U21
B5_IO[20]
R18
B5_IO[21]
R19
B5_IO[22]
N16
B5_IO[23]
R22
B5_IO[24]
R21
B5_IO[25]
P20
B5_IO[26]
P22
B5_IO[27]
P21
B5_IO[28]
N20
B5_IO[29]
N19
B5_IO[30]
N17
B5_IO[31]
N18
B5_IO[32]
N22
B5_IO[33]
N21
B5_IO[34]
M22
B5_IO[35]
M21
B5_IO[36]
M20
B5_IO[37]
M19
B5_IO[38]
M16
B5_IO[39]
T22
CLK7
T21
CLK6
3V3
R187
10K
3DTV
2010. 02. 11
3DF_INPUT/OUTPUT
1
3
LVDS OUTPUT
LVDS INPUT
<3D_SYNC_OUT>
TP[0]
TP[1]
TP[2]
TP[3]
TP[4]
TP[5]
FPGA DOWNLOAD CONTROL
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