Read LG 42PW350R-MA (CHASSIS:PU11A) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PCM_A[3]
PCM_A[0]
PCM_A[1]
PCM_A[2]
PCM_A[4]
PCM_A[6]
PCM_A[6]
PCM_A[5]
PCM_A[5]
PCM_A[7]
PCM_A[4]
PCM_A[3]
PCM_A[2]
PCM_A[1]
PCM_A[7]
PCM_A[0]
R46
22
R51
33
Q103
2SC3052
2SC3052
E
B
C
SPI_SDO
R12
1K
1K
AV_CVBS_DET
MODEL_OPT_3
UART_PM_TX
R35
1K
Q101
KRC103S
READY
KRC103S
READY
E
B
C
/SPI_CS
PWM0
5V_DET_HDMI_4
FE_TS_SYN
AMP_MUTE
R2
0
0
READY
FE_TS_SERIAL
SPI_SDO
R22
4.7K
COMP1_DET
PF_WP
UART_PM_RX
/SPI_CS
+3.3V_AVDD
EDID_WP
R41
1K
READY
AR103
22
/PF_OE
PWM1
IC102
CAT24WC08W-T
3
A2
2
A1
4
VSS
1
A0
5
SDA
6
SCL
7
WP
8
VCC
+3.3V_ST
TUNER_RESET
L102
/PF_CE0
+3.3V_AVDD
+3.3V_AVDD
C6
10uF
6.3V
R9
10K
C1
0.1uF
0.1uF
R6
4.7K
READY
R52
33
R55
33
TOUCH_VER_CHK
/PF_WE
S7_RXD
/FLASH_WP
5V_DET_HDMI_3
R7
4.7K
4.7K
AR102
22
ERROR_DET
R53
33
SPI_SDI
R97
33
+3.3V_ST
R17
1K
READY
R56
22
/PF_WE
3D_RF_RXD
R40
1K
READY
/FLASH_WP
R1
0
0
LED_WHITE
S7_TXD
R83
33
R11
4.7K
READY
IC109-*1
M24512-HRMN6TP
ST_NVRAM_512K
3
E2
2
E1
4
VSS
1
E0
5
SDA
6
SCL
7
WP
8
VCC
R80
10K
SPI_SCK
AUD_MASTER_CLK
C7 0.1uF
KEY1
+3.3V_AVDD
R24
33
READY
PF_ALE
I2C_SDA
R34
1K
READY
5V_DET_HDMI_2
MODEL_OPT_1
RGB_DDC_SCL
I2C_SDA
AC_DET
R81
33
I2C_SCL
R57
22
R82
33
PCM_A[0-7]
I2C_SCL
PWM1
MOD_ROM_TX
AUD_SCK
R4
0
R39
1K
R54
33
R20
4.7K
/F_RB
R10
1K
READY
PF_ALE
I2C_SDA
R129
22
+1.8V_ON
R3
10K
READY
RGB_DDC_SDA
R36
1K
R13
4.7K
C4
0.1uF
IC109
M24M01-HRMN6TP
3
E2
2
E1
4
VSS
1
NC
5
SDA
6
SCL
7
WP
8
VCC
SPI_SDI
SIDE_CVBS_DET
3D_RF_RESET
RL_ON
R99
1K
R18
22
READY
R37
1K
/PF_OE
R50
33
R42
1K
READY
FE_TS_VLD
/PF_CE0
R19
3.9K
R8
10K
LED_RED
5V_ON
FE_TS_CLK
3D_RF_TXD
C5
0.1uF
16V
0.1uF
16V
I2C_SCL
R16
1K
SPI_SCK
/PF_CE1
IC104
NAND01GW3B2CN6E
26
NC_17
27
NC_18
28
NC_19
29
I/O0
30
I/O1
31
I/O2
32
I/O3
33
NC_20
34
NC_21
35
NC_22
36
VSS_2
37
VDD_2
38
NC_23
39
NC_24
40
NC_25
41
I/O4
42
I/O5
43
I/O6
44
I/O7
45
NC_26
46
NC_27
47
NC_28
48
NC_29
17
AL
3
NC_3
6
NC_6
16
CL
15
NC_10
14
NC_9
13
VSS_1
12
VDD_1
11
NC_8
10
NC_7
9
E
8
R
7
RB
4
NC_4
5
NC_5
25
NC_16
24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
W
PF_WP
R38
1K
KEY2
PCM_A[0-7]
C19
10pF
READY
C3
0.1uF
IC103-*1
MX25L8006EM2I-12G
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
+3.3V_AVDD
LGE101D (S7 Non_Tcon/RM)
IC101
S7R
PCM_D0
U22
PCM_D1
T21
PCM_D2
T22
PCM_D3
AB18
PCM_D4
AC18
PCM_D5
AC19
PCM_D6
AC20
PCM_D7
AC21
PCM_A0
U21
PCM_A1
V21
PCM_A2
Y22
PCM_A3
AA22
PCM_A4
R22
PCM_A5
R21
PCM_A6
T23
PCM_A7
T24
PCM_A8
AA23
PCM_A9
Y20
PCM_A10
AB17
PCM_A11
AA21
PCM_A12
U23
PCM_A13
Y23
PCM_A14
W23
PCM_REG_N
W22
PCM_OE_N
AA17
PCM_WE_N
V22
PCM_IORD_N
W21
PCM_IOWR_N
Y21
PCM_CE_N
AA20
PCM_IRQA_N
V23
PCM_CD_N
P23
PCM_WAIT_N
R23
PCM_RESET
P22
PCM_PF_CE0Z
AC17
PCM_PF_CE1Z
AB20
PCM_PF_OEZ
AA18
PCM_PF_WEZ
AB21
PCM_PF_ALE
AB19
PCM_PF_AD[15]
AD17
PCM_PF_RBZ
AA19
UART_TX2/GPIO65
M23
UART_RX2/GPIO64
N23
DDCR_DA/GPIO71
M22
DDCR_CK/GPIO72
N22
DDCA_DA/UART0_TX
A5
DDCA_CK/UART0_RX
B5
PWM0/GPIO66
K23
PWM1/GPIO67
K22
PWM2/GPIO68
G23
PWM3/GPIO69
G22
PWM4/GPIO70
G21
SAR0/GPIO31
C6
SAR1/GPIO32
B6
SAR2/GPIO33
C8
SAR3/GPIO34
C7
SAR4/GPIO35
A6
TCON0/POL
N21
TCON2/GSP_R/GCLK1
M21
TCON4/CPV/GSC/GCLK3
L22
TCON6/FLK
L21
TCON8/CS2/FLK3
P21
GPIO36/UART3_RX
K21
GPIO37/UART3_TX
L23
GPIO38
K20
GPIO39
L20
GPIO40
M20
GPIO41
G20
GPIO42
G19
GPIO50/UART1_RX
F20
GPIO51/UART1_TX
F19
GPIO6/PM0/INT0
E7
GPIO7/PM1/PM_UART_TX
D7
GPIO8/PM2
E11
GPIO9/PM3
G9
GPIO10/PM4
F9
GPIO11/PM5/PM_UART_RX/INT1
C5
PM_SPI_CS1/GPIO12/PM6
E8
PM_SPI_WP1/GPIO13/PM7
E9
PM_SPI_WP2/GPIO14/PM8/INT2
F7
GPIO15/PM9
F6
PM_SPI_CS2/GPIO16/PM10
D8
GPIO17/PM11/INT3
G12
GPIO18/PM12/INT4
F10
PM_SPI_CK/GPIO1
D9
GPIO0/PM_SPI_CZ
D11
PM_SPI_DI/GPIO2
E10
PM_SPI_DO/GPIO3
D10
TS0_CLK
AA9
TS0_VLD
AA5
TS0_SYNC
AA10
TS0_D0
AB5
TS0_D1
AC4
TS0_D2
Y6
TS0_D3
AA6
TS0_D4
W6
TS0_D5
AA7
TS0_D6
Y9
TS0_D7
AA8
TS1_CLK
AC5
TS1_VLD
AC6
TS1_SYNC
AB6
TS1_D0
AC10
TS1_D1
AB10
TS1_D2
AC9
TS1_D3
AB9
TS1_D4
AC8
TS1_D5
AB8
TS1_D6
AC7
TS1_D7
AB7
MPIF_CLK
D12
MPIF_CS_N
D14
MPIF_BUSY
E14
MPIF_D0
E12
MPIF_D1
F12
MPIF_D2
D13
MPIF_D3
E13
MOD_ROM_RX
AUD_LRCH
R33
1K
READY
C18
10pF
READY
R98
33
IC103
MX25L8005M2I-15G
15G
3
WP#
2
SO
4
GND
1
CS#
5
SI
6
SCLK
7
HOLD#
8
VCC
/F_RB
/PF_CE1
PWM0
+3.3V_ST
R92
33
1 14
EAX63425901(8)
S7/FLASH/NVRAM/GPIO
<T3 CHIP Config(AUD_LRCH)>
1M BIT EEPROM
H : JEIDA
V4 LGD BIT SEL
L or NC : VESA
V4 LGD LVDS SEL
AFLC: LED TV OPTION
I2C : A0
V4 LGD OPC
PWM2
4.CHIP_CONF= 4’hB:{1,0,1,1}B51_Secure_no_scramble
OPC: Optimal power control FOR PICTURE
<CHIP_CONF={AUBCK_OUT,AUMCK_OUT,PWM1,PWM0}>
H : ENABLE
2.CHIP_CONF= 4’h4:{0,1,0,0}MIPS_EJ1_NOR8
L or NC : DISABLE
3.CHIP_CONF= 4’h5:{0,1,0,1}MIPS_EJ2_NOR8
/PF_CE0
H : Serial Flash
L : NAND Flash
/PF_CE1
H : 16 bit
L : 8 bit
H : Serial Flash
L : NAND Flash
/PF_CE1
H : 16 bit
L : 8 bit
1.CHIP_CONF= 4’h3:{0,0,1,1}MIPS_no_EJ_NOR8
BIT_SEL,LVDS_SE : LCD MODULE OPT
8K BIT HDCP EEPROM
5.CHIP_CONF= 4’hC:{1,1,0,0}B51_Secure_scramble
512KBIT = $0.35
L : 8 bit
2.MIPS as host,EJ use PAD1,Byte mode NAND flash
BRAZIL DEMOD OPT
H or NC : 10 bit
1.MIPS as host(8051’s reset remains until MIPS deactive it.),No EJ PAD,Byte mode NAND flash
S7 IC Configuration
3.MIPS as host,EJ use PAD2,Byte mode NAND flash
Boot from SPI flash : 1’b0
Boot from NOR flash : 1’b1
Boot from NOR flash : 1’b1
8M BIT serial Flash
CH_2
CH_8
CH_2
CH_2
Serial FLASH MEMORY
for BOOT
for BOOT
Addr:10101--
$0.199
S7R
2010.09.14
2G BIT NAND Flash
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