Read LG 32LD650H (CHASSIS:LD03Z) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LD1301
A2[RD]
C
A1[GN]
1K
R1330
18pF
50V
C1318
0 . 1 u F
C1328
1K
OPT
R1344
BLM18PG121SN1D
L1301
0 . 1 u F
C1334
D3.3_ETHUB
270
1%
R1315
SETGROUP
D1.8_ETHUB
0 . 1 u F
C1329
EPHY_TXON3
0
R1312
GYFULL
LAN_LINK0
EN_AUTOXOVER
0 . 1 u F
C1327
0 . 1 u F
16V
C1312
EPHY_TXOP1
4 9 . 9
1%
1%
R1321
1K
OPT
R1347
PHY2PTXEN
EPHY_RXIN1
A1.8_ETHUB
LAN_LINK2
0 . 1 u F
C1343
1.69K
1%
R1316
0 . 1 u F
C1338
0 . 1 u F
C1342
0 . 1 u F
C1346
0 . 1 u F
16V
16V
C1313
330
R1327
GXFULL
4 9 . 9
1%
1%
R1311
22uF
16V
16V
C1336
1K
OPT
R1348
1K
OPT
R1350
0 . 1 u F
C1333
EPHY_ACTIVITY
470
R1335
22uF
16V
16V
C1345
0 . 1 u F
C1321
GYFULL
33
R1323
1K
OPT
R1334
33
R1322
LD1300
A2[RD]
C
A1[GN]
0 . 1 u F
C1323
AUTO_NEGO
1K
OPT
R1352
1K
R1331
1K
R1342
4 9 . 9
1%
1%
R1309
10K OPT
R1339
A3.3_ETHUB
D1.8_ETHUB
0 . 1 u F
C1325
0
R1353
1K
R1317
LD1303
A2[RD]
C
A1[GN]
EPHY_TDN
GXMODE
1K
OPT
R1345
1K
R1333
EN_AUTOXOVER
10K OPT
R1338
CIS21J121
L1305
25MHz
X1300
1K
OPT
R1349
4 9 . 9
1%
1%
R1308
330
R1325
A1.8_ETHUB
EPHY_RXIP1
0 . 1 u F
C1340
EPHY_RDN
0 . 1 u F
C1330
EPHY_RXIP3
0 . 1 u F
16V
C1315
LAN_ACT3
LAN_ACT1
D3.3_ETHUB
1K
OPT
R1346
EPHY_TXON0
EPHY_LINK
ETHUB_MDC
PHY2PRXD3
330
R1324
10K OPT
R1337
LAN_ACT3
AUTO_NEGO
22uF
16V
16V
C1303
DUP3_GYMODE
0 . 1 u F
C1337
4 9 . 9
1%
1%
R1310
18pF
50V
C1317
LAN_ACT0
ENDEFER
GXFULL
GXMODE
22uF
16V
16V
C1341
ENDEFER
ETHUB_RESET
P4MODE0
P4MODE0
A3.3_ETHUB
10K
OPT
R1340
DISDUALMII
EPHY_RDP
22uF
16V
16V
C1311
BLM18PG121SN1D
L1304
EPHY_TXON3
GXSPD
0
R1313
GYSPD
EPHY_RXIN3
PHY2PRXDV
PHY2PRXDV
22uF
16V
16V
C1308
D2.5V_ETHUB
A1.8_ETHUB
D3.3_ETHUB
ETHUB_MDIO
SETGROUP
EPHY_TXOP3
0 . 1 u F
C1335
LAN_LINK1
22uF
16V
16V
C1316
1K
OPT
R1355
470
R1336
DISDUALMII
LAN_ACT2
P4MODE1
LAN_LINK2
GXSPD
EPHY_TXON1
EPHY_RXIN3
GYSPD
DUP3_GYMODE
LAN_LINK0
22uF
16V
16V
C1300
LD1302
A2[RD]
C
A1[GN]
PHY2PTXEN
0 . 1 u F
C1332
LAN_ACT0
1K
OPT
R1341
CIS21J121
L1306
0 . 1 u F
C1319
0 . 1 u F
16V
16V
C1320
4 9 . 9
1%
1%
R1319
LAN_ACT2
EPHY_TDP
PHY2PRXD3
EPHY_TXOP3
330
R1326
A1.8_ETHUB
22uF
16V
16V
C1314
OPT
0 . 1 u F
C1326
1K
OPT
R1351
0 . 1 u F
16V
C1304
0
R1314
0
R1354
0
R1328
0 . 1 u F
C1339
1K
OPT
R1343
D1.8_ETHUB
470
OPT
R1332
LAN_LINK3
4 9 . 9
1%
1%
R1320
1M
R1307
EPHY_RXIP3
4 9 . 9
1%
1%
R1318
0 . 1 u F
C1322
0 . 1 u F
C1324
D3.3_ETHUB
D3.3_ETHUB
0 . 1 u F
C1331
0 . 1 u F
C1344
EPHY_TXOP0
P4MODE1
EPHY_RXIN0
EPHY_RXIP0
LAN_ACT3
LAN_LINK3
+3.5V_ST
0
R1304
BLM18PG121SN1D
L1303
BLM18PG121SN1D
L1300
A2.5V
LAN_LINK0
LAN_ACT0
LD1304
A2[RD]
C
A1[GN]
LD1305
A2[RD]
C
A1[GN]
D3.3_ETHUB
330
R1300
330
R1301
Ethernet_RX_DB-
Ethernet_TX_DA-
Ethernet_TX_DA+
Ethernet_RX_DB+
4 9 . 9
1%
1%
R1306
0 . 1 u F
C1310
0 . 1 u F
C1309
4 9 . 9
1%
1%
R1302
0 . 1 u F
C1302
CIS21J121
L1302
A1.8_ETHUB
EPHY_TXON0
0 . 1 u F
C1301
EPHY_RXIN0
EPHY_TXOP0
0 . 1 u F
C1307
4 9 . 9
1%
1%
R1303
4 9 . 9
1%
1%
R1305
0 . 1 u F
C1305
EPHY_RXIP0
D2.5V_ETHUB
10K
R1364
THERMAL
MP20045DQ-LF-Z
IC1302
3
VOUT_1
2
VIN_2
4
VOUT_2
1
VIN_1
5
FB
6
GND
7
PG
8
EN
9
EP[GND]
RSR025P03
Q1300
S
D
G
10K
R1360
ETHUB_PWR_ON/OFF
10K
R1361
OPT
10K
R1362
100K
R1363
CIC21J501NE
L1307
2K
R1365
A3.3_ETHUB
A3.3_ETHUB
RTL8306G
IC1300
1
AVDD18_1
2
RXIN[0]
3
RXIP[0]
4
AGND_1
5
TXOP[0]
6
TXON[0]
7
AVDD18_2
8
AVDD18_3
9
TXON[1]
10
TXOP[1]
11
AGND_2
12
RXIP[1]
13
RXIN[1]
14
AVDD18_4
15
AVDD18_5
16
RXIN[2]
17
RXIP[2]
18
AGND_3
19
TXOP[2]
20
TXON[2]
21
AVDD18_6
22
AVDD18_7
23
TXON[3]
24
TXOP[3]
25
AGND_4
26
RXIP[3]
27
RXIN[3]
28
AVDD18_8
29
AVDD18_9
30
RXIN[4]
31
RXIP[4]
32
AGND_5
33
TXOP[4]
34
TXON[4]
35
AVDD18_10
36
ITEST1
37
ITEST2
38
ITEST3
39 DGND_1
40 RESET#
41 ITEST4
42
DISDUALMII(MODESET4)
43 DVDD18_1
44
P4MODE[1](MODESET3)
45
P4MODE[0](MODESET2)
46P4FLCTRL/CPU_INTERRUPT#
47 P4SPDSTA
48
P4DUPSTA/HOME_CRS
49P4LNKSTA#
50 DGND_2
51
MTXC/PRXC/CTRL_REFCLK1
52M(R)TXEN/PRXDV
53 DVDD18_2
54
M(R)TXD[0]/PRXD[0]/LEDMODE[0]
55
M(R)TXD[1]/PRXD[1]/LEDMODE[1]
56
MTXD[2]/PRXD[2]/P4IRTAG[0]
57
MTXD[3]/PRXD[3]/P4IRTAG[1]
58MCOL/PCOL
59
MRXC/PTXC/REFCLK1
60
MRXDV/PTXEN/CRSDV
61
M(R)RXD[0]/PTXD[0]
62 DVDD33_1
63
M(R)RXD[1]/PTXD[1]
64 DGND_3
65
ITEST5
66
MRXD[2]/PTXD[2]
67
MRXD[3]/PTXD[3]
68
SEL_MIIMAC#/DISDSPRI
69
EN_AUTOXOVER
70
DVDD18_3
71
EN_RST_BLNK
72
ITEST6
73
PHY2PRXD[0]/M(R)2TXD[0]/ENEEPROM
74
SCL_MDC
75
SDA_MDIO
76
PHY2PRXD[1]/M(R)2TXD[1]/GXENFC
77
PHY2PRXD[2]/M2TXD[2]/GYENFC
78
PHY2PRXD[3]/M2TXD[3]/ENBKPRS
79
DGND_4
80
PHY2PRXDV/M(R)2TXEN/DISBRDCTRL
81
PHY2PRXC/M2TXC/CTRL_REFCLK2
82
PHY2PTXC/M2RXC/REFCLK2
83
DISPORTPRI[0]/PHY2PTXEN/M2RXDV/CRSDV2
84
DISPORTPRI[1]/PHY2PTXD[0]/M(R)2RXD[0]
85
DISPORTPRI[2]/PHY2PTXD[1]/M(R)2RXD[1]
86
DISPORTPRI[3]/PHY2PTXD[2]/M2RXD[2]
87
DVDD33_2
88
DISPORTPRI[4]/PHY2PTXD[3]/M2RXD[3]
89
PHY2PCOL/M2COL/LED_BLNK_TIME
90
LOOPLED#/ENDEFER
91
LED_ADD[4]/DISTAGPRI
92
LED_ACT[4]/DISHOMEPLUG
93
LED_SPD[4]/DISVLAN
94
DGND_5
95
LED_DUP[4]/SETGROUP
96
LED_ADD[3]/MODESET1
97
LED_ACT[3]/EN48PASS1
98
LED_SPD[3]/DISARP
99
LED_DUP[3]/MODESET0
100
DVDD18_4
101
LED_ADD[2]/DISLEAKY
102
DGND_6
103
LED_ACT[2]/P4ANEG
104
LED_SPD[2]/GXANEG
105
LED_DUP[2]/GYANEG
106
DVDD33_3
107
LED_ADD[1]/GXSPD100
108
LED_ACT[1]/GYSPD100
109
LED_SPD[1]/GXFULL
110
LED_DUP[1]/GYFULL
111
LED_ADD[0]/ENFORWARD
112
DGND_7
113
LED_ACT[0]/BCINDROP
114
LED_SPD[0]/MAX1536
115
LED_DUP[0]
116
CK25MOUT
117
OSCI
118
HVDD33
119
AVDD18_11
120
X1
121
X2
122
AGND_6
123
VCTRL
124
DTEST2
125
DTEST1
126
AGND_7
127
IBREF
128
AVDD18_12
1K
R1368
2SC3052
Q1301
E
B
C
2 . 2 u F
25V
25V
C1348
2 . 2 u F
25V
25V
C1349
ETHUB_MDC
ETHUB_MDIO
1K
R1329
1K
R1357
1K
R1358
OPT
1K
R1359
OPT
D3.3_ETHUB
P l a c e c l o s e t o c h i p
P l a c e t o c e n t e r p o s i t i o n b e t w e e n t w o c h i p s
BCM
CONFIG FOR MAC5
FOR DEBUG
D i f f e r e n t i a l 1 0 0 o h m
N o V i a
C l o s e t o
P l a c e c l o s e t o c h i p
P H Y 2 P R X D V : B r o a d c a s t s t r o m c o n t r o l e n a b l e / d i s a b l e
P H Y 2 P R X D 3 : B a c k p r e s s u r e e n a b l e / d i s a b l e
E N D E F E R : D e f e r e n a b l e / d i s a b l e
EN_AUTOXOVER : Auto cross over enable/disable
P l a c e C l o s e T o R T L 8 3 0 6
P l a c e C l o s e T o R T L 8 3 0 6
STRAPPING PIN CONFIG
RTL
Chameleon(EU_GP2_BCM3556)
13
xxLD650H-ZA
2 0 1 0 . 0 2 . 0 4
ETHERNET HUB
NEW MPI
P l a c e t o c e n t e r p o s i t i o n b e t w e e n t w o c h i p s
P l a c e c l o s e t o c h i p
BCM TO RTL matching
MPI TO RTL matching
$ 0 . 1 3
V o u t = 1 . 5 * ( 1 + R 1 / R 2 )
R1
R2
Vout
Click on the first or last page to see other 32LD650H (CHASSIS:LD03Z) service manuals if exist.