AVR 265 (serv.man5) - Harman Kardon Audio Service Manual (repair manual). Page 123

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Data Sheet
8 Mbit SPI Serial Flash
SST25VF080B
3
©2006 Silicon Storage Technology, Inc.
S71296-01-000
1/06
PIN DESCRIPTION
FIGURE 1: P
IN
 A
SSIGNMENTS
TABLE
1: P
IN
 D
ESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, 
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin. 
See “Hardware End-of-Write Detection” on page 12 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the 
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the 
device.
V
DD
Power Supply
To provide power supply voltage: 2.7-3.6V for SST25VF080B
V
SS
Ground
T1.0 1296
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD 
HOLD#
SCK
SI
Top View
1296 08-soic S2A P1.0
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1296 08-wson QA P2.0
8-
LEAD
 SOIC
8-
CONTACT
 WSON
Harman Kardon
AVR 265/230V Service Manual
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