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9
DP-3520/4520/6020
DP-3510/4510/6010
NOV 2003
Ver. 4.00
3. Reset Circuit
This Circuit is controlled by the Reset of IC6 (PST575E) and nPRST Signal from the SC PCB.
If the 5 VDC Power Voltage becomes lower than 3.9 VDC, this circuit generates a Reset Signal. If the
nPRST signal from the SC PCB is Low, this Circuit also generates a Rest Signal.
If the 5 VDC Power Voltage becomes lower than 3.9 VDC, this circuit generates a Reset Signal. If the
nPRST signal from the SC PCB is Low, this Circuit also generates a Rest Signal.
4. DRIVER PCB (DRV PCB) Interface
The interface uses FIFO with DRV PCB via Serial data.
IC6
PST575E
nPRST
IC1
M30802
R95
C47
R97
Q3
IC10
5V
3. 9V
td
td
td =12.5ms
+5V
IC5
GATE ARRAY
SPC
DRV
IC7
M66313
DO
UT
CLK
LATCH
ENABLE
LOAD
nGARST
A
CK
nLE
IC4
IC4
IC4
IC4
IC4
nOE
nSD
IC9
74VHC165
CLK
SH/nLD
Qn
IC10
74VHC165
CLK
SH/nLD
Qn
IC11
74VHC165
CLK
SH/nLD
Qn
IC12
74VHC165
CLK
SH/nLD
nQn
SER
SER
SER
SER
IC5
IC5
DIN
IC7
IC7
IC7
IC7
IC7
IC7
IC8
DOUT
CLK
LATCH
LD
DIN
1
2
3
4
5
6
7
8
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