KE-42TS2E, KE-42TS2U - Sony TV Service Manual (repair manual). Page 8

  

 

  

 

 

 

 

5

（３） Video Signal Definition and Function 

The table below summarizes the definitions and functions of input video signals before  
LVDS conversion. 

 

Item 

Signal name 

Number 

of 

signal

s 

Input/
output

Signal definition and function 

Video signal 
(digital RGB) 

DATA-R 
DATA-G 
DATA-B 

8 
8 
8 

Input

Display data signal 
R7/G7/B7 is the highest intensity bit.
R0/G0/B0 is the lowest intensity 
bit. 

Data Clock 

 
DCLK 

１ Input

Display data timing signal: Data are 
read when DCLK is low. DCLK is 
continuously input. 

Horizontal 
sync signal 

_____ 
Hsync 

1 Input

Regulates one horizontal line of data: 
Begins control of the next screen when 
Hsync is lowered. 

Vertical sync 
signal 

_____ 
Vsync 

1 Input

Screen starts up control timing signal:
Begins control of the next screen when
Vsync is lowered.                     
Input the same frequency in both 
odd-numbered and even-numbered fields.

Parity signal 

PARITY 

1 Input

This signal specifies the display 

field.   

    H:  Odd-numbered field   
    L:  Even-numbered field           

Parity signal should be alternated in 
every Vsync cycle. 

Original 
Display 
signal  
(before 
LVDS 
transmit
tance) 

Blanking 
signal 

  
BLANK  

1 Input

Display period timing signal. 
H indicates the display period and L 
indicates the non display period. 
Note: 
Set this timing properly like 
followings, as is used internally for 
signal processing. 
・Set the blanking period so that the 
number of effective display data items 
in one horizontal period is 852. 
・Set the number of blanking signals in 
one vertical period to 512, which is 
one half the number of effective scan 
lines. 
If the BLANK changes when the Vsync 
frequency is switched, the screen 
display may be disturbed or brightness 
may change. 
The screen display is restored to the 
normal state later when the BLANK 
length is constant again. 

＊１）This product does not correspond to the progressive display mode by the parity signal fixation. 

When the parity signal is fixed, this product is reversed arbitrarily internally and used.