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3-3-2. Y-Main
board
The Y-MAIN board generates a drive signal by switching the FET in synchronization
with the Logic Main board timing, and sequentially supplies the Y electrode of the
panel with the drive signal through the scan driver IC on the Y-buffer board. This
board, connected to the panel’s Y terminal, has the following main functions:
1) Maintain voltage waveforms (including ERC).
2) Generate Y Rising Ramp signal.
3) Maintain Vscan bias.
3-3-3. Logic Main board
The Logic Main board generates and outputs the address drive output signal and the
XY drive signal by processing the video signals. This board buffers the address drive
output signal and feeds it to the address driver IC (COF module).
(Video signal processing – XY drive signal generation - frame memory control –
address/data rearrangement – system control)
3-3-4. Logic buffer (E, F)
The logic buffer transmits data signals and control signals using a COF (Chip on
Flexible).
3-3-5. Y-buffer board (upper/lower)
The Y-buffer board consisting of the upper and lower boards supplies the Y terminal
with a scan waveform. The board comprises eight scan driver ICs (STMicroelectronics
STV7617: 64 or 65 output pins), but four ICs for the SD Class.
3-3-6. COF (Chip on Flexible)
The COF applies Va pulse to the address electrode, and constitutes address
discharge by the potential difference between the Va pulse and the pulse applied to
the Y electrode. The COF comprises four data driver ICs (STV7610A: 96 output pins).
Seven COFs are required for single scan.
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