KE-37XS910, KE-42XS910, KE-MX37A1, KE-MX37N1, KE-MX37S1 - Sony TV Service Manual (repair manual). Page 10

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(3) Video Signal Definition and Function 
The table below summarizes the definitions and functions of input video signals before LVDS 
conversion. 
 
Item 
Signal name 
Number 
of signals 
Input/ 
output 
Signal definition and function 
Video signal 
(digital RGB) 
DATA-R 
DATA-G 
DATA-B 
10 
10 
10 
Input 
Display data signal 
R9/G9/B9 is the highest intensity bit. 
R0/G0/B0 is the lowest intensity bit. 
Data Clock 
DCLK  
 Input 
Display data timing signal: Data are read when 
DCLK  is lowerd.  DCLK  is continuously 
input. 
Horizontal 
sync signal 
Hsync  
1 Input 
Regulates one horizontal line of data: Begins 
control of the next screen when  Hsync  is 
lowered. 
Vertical sync 
signal 
Vsync  
1 Input 
Screen starts up control timing signal: Begins 
control of the next screen when  Vsync  is 
lowered.                                                                 
Input the same frequency in both 
odd-numbered and even-numbered fields. 
Parity signal 
PARITY  
Input 
This signal specifies the display field.     
    H: Odd-numbered field 
    L: Even-numbered field 
Parity signal should be alternated in every 
Vsync  cycle. 
Original 
Display signal   
(before LVDS 
transmittance) 
Blanking 
signal 
BLANK  
1 Input 
Display period timing signal. 
H indicates the display period and L indicates 
the non display period. 
Note: 
Set this timing properly like followings, as is 
used internally for signal processing. 
Set the blanking period so that the number of 
effective display data items in one horizontal 
period is 1024. 
Set the number of blanking signals in one 
vertical period to 512, which is one half the 
number of effective scan lines. 
If the  BLANK   changes when the  Vsync  
frequency is switched, the screen display may 
be disturbed or brightness may change. 
The screen display is restored to the normal 
state later when the  BLANK  length is 
constant again. 
*This product does not correspond to the progressive display mode by the parity signal fixation. 
When the parity signal is fixed, this product is reversed arbitrarily internally and used. 
 
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