Read Sony KDL-32T2800 / KDL-40T2800 Service Manual online
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~ BC Board Schematic Diagram [ Tuner, Audio/Video Processor, HDMI & PC Input ] Page 6/13 ~
0 . 1
C5040
C5024
0 . 1
0 . 1
C5026
10k
R5016
0 . 1
C5028
0.1
C5020
0 . 1
C5027
0 . 1
C5031
0 . 1
C5039
0 . 1
C5043
0 . 1
C5033
1608
16V
0 . 1
B
C5034
3.3V_MAIN
0 . 1
C5030
0.1
C5019
0 . 1
C5044
0 . 1
C5029
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
29
28
27
26
25
24
23
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
IC5001
XX
TD5
GND
TD6
TE0
TE1
TE2
VCC
TE3
TE4
GND
TE5
CLK IN
/PDWN
PLL GND
PLL VCC
TE6
LVDS GND
TE+
TE-
TD+
TD-
TCLK+
TCLK-
TC+
TC-
LVDS GND
LVDS VCC
TB+
TB-
TA+
TA-
LVDS GND
TA0
TA1
TA2
TA3
TA4
TA5
GND
TA6
TB0
TB1
RS
TB2
TB3
TB4
GND
TB5
TB6
TC0
VCC
TC1
TC2
TC3
TC4
GND
TC5
TC6
TD0
R/F
TD1
TD2
TD3
TD4
10k
R5017
10k
R5015
8765
4
3
2
1
IC5003
nCS
DATA
VCC
GND
ASDI
DCLK
VCC
VCC
1608
16V
0 . 1
B
C5022
0 . 1
C5032
0 . 1
C5042
0 . 1
C5023
0 . 1
C5041
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
IC5002
IO/ASDO
IO/nCSO
IOLVDS15p/CRC_ERROR
IO/LVDS15n/CLKUSR
VCCIO1
GND
IO/VREFB1N0
IO/LVDS8p
IO/LVDS8n
TDO
TMS
TCK
TDI
DATA0
DCLK
nCE
CLK0/VDSCLK0p/input(3)
CLK1/VDSCLK0n/input(3)
GND
nCONFIG
CLK2/VDSCLK1p/input(3)
CLK3/VDSCLK1n/input(3)
VCCIO1
IO/LVDS7p
IO/LVDS7n
VCCINT
GND
IO/VREFB1N1
VCCIO1
IO
IO/PLL1_OUTp
IO/PLL1_OUTn
GND
GND_PLL1
VCCD_PLL1
GND_PLL1
VCCA_PLL1
GNDA_PLL1
GND
IO/LVDS77n/DEV_OE
IO/LVDS77p
OI/LVDS76p
IO/LVDS76n
IO/LVDS75p
IO/LVDS75n
VCCIO4
IO/LVDS74p
IO/LVDS74n
GND
VCCINT
IO/VREFB4N1
IO/LVDS70p
IO/LVDS68p
VCCIO4
IO/LVDS68n
GND
IO/LVDS67p
IO/LVDS67n
IO/LVDS66p
IO/LVDS66n
GND
VCCINT
IO/VREFB4N0
IO/LVDS60p
IO/LVDS60n
VCCIO4
IO/LVDS59n
GND
IO/LVDS58p
IO/LVDS58n
IO/LVDS57p
IO/LVDS57n
IO/LVDS56n
IO/LVDS56p
IO/LVDS54n/INIT_DONE
IO/LVDS54p/nCEO
VCCIO3
GND
IO/VREFB3N1
GND
VCCINT
nSTATUS
CONF_DONE
MSEL1
MSEL0
IO/LVDS48n
IO/LVDS48p
CLK7/LVDSCLK3n/input(3)
CLK6/LVDSCLK3p/input(3)
CLK5/LVDSCLK2n/input(3)
CLK4/LVDSCLK2p/input(3)
IO/LVDS47n
IO/LVDS47p
IO/LVDS46n
VCCIO3
IO/LVDS46p
IO/LVDS45n
GND
IO/VREFB3N0
IO/LVDS39n
IO/LVDS39p
VCCIO3
IO/PLL2_OUTp
IO/PLL2_OUTn
GND
GND_PLL2
VCCD_PLL2
GND_PLL2
VCCA_PLL2
GNDA_PLL2
GND
IO/LVDS37n
IO/LVDS37p
IO/LVDS36n
IO/LVDS36p
VCCIO2
GND
IO/LVDS34n
IO/LVDS34p
IO/VREFB2N0
IO/LVDS33n
IO/LVDS33p
GND
VCCINT
IO/LVDS29n
IO/LVDS29p
VCCIO2
GND
IO/LVDS26p
GND
VCCINT
IO/VREFB2N1
IO/LVDS23n
IO/LVDS23p
IO/LVDS19n
IO/LVDS19p
IO/LVDS18n
VCCIO2
IO/LVDS18p
GND
IO/LVDS17p
IO/LVDS17n/DEV CLRn
IO/LVDS16p
IO/LVDS16n
0 . 1
C5035
1/10W
RN-CP
5%
100k
R5007
1608
16V
0 . 1
B
C5013
1608
16V
0 . 1
B
C5014
1608
25V
0 . 0 1
B
C5009
2012
6.3V
10
B
C5012
1608
16V
0 . 1
B
C5011
1608
25V
1000p
CH
C5008
1608
25V
1000p
CH
C5005
1608
16V
0 . 1
B
C5007
2012
6.3V
10
B
C5010
1608
25V
0 . 0 1
B
C5006
XX
L5007
1608
16V
0 . 1
B
C5015
1/10W
RN-CP
5%
10k
R5011
CHIP
0
R5008
3.3V_MAIN
FPGA_2_LVDSTX
FPGA_2_LVDSTX
100
C5046
1.2V_MAIN
100
C5045
0 . 1
C5021
1000p
C5025
1uH
L5008
10
C5018
1000p
C5036
0 . 1
C5037
10
C5038
1uH
L5009
FPGA_RESETQ
VIDEO_VCTP_2_FPGA
CLKIN_2025
10
RB5009
10
RB5010
10
RB5011
10
RB5012
10
RB5015
10
RB5014
10
RB5013
10
RB5017
10
RB5016
SCL
SDA
R5022
100
R5023
100
CLKIN_2025
JL5017
JL5020
JL5021
JL5002
JL5003
JL5001
JL5011
JL5012
JL5013
JL5014
JL5015JL5016
4
12
3
0uH
L5003
4
12
3
L5006
0uH
4
12
3
0uH
L5005
4
12
3
0uH
L5002
4
12
3
0uH
L5004
4
12
3
0uH
L5001
JL5008
JL5004
R5012
XX
R5009
XX
XX
R5018
JL5005
JL5006
JL5007
JL5010
JL5022
JL5023
FPGA_CONF_DONE
JL5024
CHIP
0
R5024
CHIP
0
R5025
CHIP
0
R5026
CHIP
0
R5027
R5030
0
R5031
0
R5032
0
R5033
0
XX
C5048
47
R5013
100
R5019
0uH
L5050
PANEL12V_LCD
XX
C5050
XX
C5051
16V
47
C5052
1608
25V
0 . 0 1
B
C5055
1608
50V
1000p
B
C5053
CHIP
0
R5053
CHIP
0
R5052
PANEL12V_GND
CHIP
0
R5055
CHIP
0
R5054
1608
CHIP
R5050
0
1608
50V
470p
B
C5054
1608
CHIP
R5051
0
XX
L5010
XX
L5011
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CN5001
GND
DCLK
nCONFIG
ASDI
CONF_DONE
GND
NC
VCC
VCC
NC
nCE
nCS
DATAOUT
GND
CHIP
0
JR5002
JR5000
0
JR5001
0
R5057
0
R5058
0
R5059
0
FPGA_CONFIG
0
R5060
XX
R5061
R5010
XX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
30P
CN5000
WHT
DCC1_DCC2/I2C_CLK(HFR)
VIN
VIN
DCC_LUT/I2C_DATA(HFR)
VIN
DCC/HF_CONT(HFR)
GND
NC/RE+
GND
NC/RE-
GND
RD+
VIN
RD-
VIN
RCLK+
GND
RCLK-
GND
RC+
GND
RC-
GND
RB+
GND
RB-
NC/12V_CONT(HFR)
RA+
GND
RA-
CHIP
0
JR5007
0
JR5010
0
JR5011
XX
RB5000
2
1
4
3
6
5
8
7
XX
RB5003
2
1
4
3
6
5
8
7
RN-CP
100
R5006
1/10W
5%
3.3V_MAIN
0 . 1
C5056
0 . 1
C5057
0 . 1
C5058
0 . 1
C5059
RB5026
XX
2
1
4
3
RB5020
XX
2
1
4
3
6
5
8
7
RB5023
XX
2
1
4
3
6
5
8
7
RB5024
XX
2
1
4
3
6
5
8
7
FPGA_2_LVDSTX_AR
RB5025
XX
2
1
4
3
6
5
8
7
VIDEO_VCTP_2_FPGA
RB5018
XX
2
1
4
3
6
5
8
7
RB5022
XX
2
1
4
3
6
5
8
7
RB5021
XX
2
1
4
3
6
5
8
7
1608
CHIP
R5056
XX
RB5019
XX
2
1
4
3
6
5
8
7
FPGA_2_LVDSTX_AR
TP5025
TP5026
TP5027
TP5028
TP5029
TP5030
TP5031
XX
C5060
FPGA_NOT_BYPASS
RB5007
XX
2
1
4
3
6
5
8
7
RB5002
XX
2
1
4
3
6
5
8
7
RB5006
XX
2
1
4
3
6
5
8
7
RB5008
XX
2
1
4
3
6
5
8
7
RB5001
XX
2
1
4
3
6
5
8
7
RB5004
XX
2
1
4
3
6
5
8
7
RB5005
XX
2
1
4
3
6
5
8
7
FPGA_2_LVDSTX
FPGA_2_LVDSTX_AR
TP5032
TP5033
TP5001
XX
R5062
GND_1
GND_1
GND_1
DRO1
DGO0
DGO1
DBO0
DBO1
DRO0
GND_1
GND_1
PCLKOUT
GND_1
GND_1
DBO1
DBO0
DGO1
DGO0
DRO1
DRO0
DBO3
DBO2
DGO2
DRO3
DRO2
DEN_OUT
DEN_OUT
DVS_OUT
DVS_OUT
DHS_OUT
DBO9
DBO8
DBO7
DBO6
DBO5
DBO4
DGO9
DGO8
DGO7
DGO6
DGO5
DGO4
DRO9
DRO8
DRO7
DRO6
GND_1
GND_1
GND_1
GND_1
GND_1
GND_1
GND_1
DRO5
GND_1
GND_1
PORT_A_A2_B2
PORT_A_A1_B1
PORT_A_A0_B0
PORT_A_DE
PORT_A_VSYNCPORT_A_VSYNC
PORT_A_HSYNCPORT_A_HSYNC
PORT_A_A3_B3
PORT_A_A4_B4
PORT_A_A5_B5
PORT_A_A6_B6
PORT_A_A8_B8
PORT_A_A9_B9
PORT_A_A7_B7
PORT_A_A13_G3
PORT_A_A12_G2
PORT_A_A11_G1
PORT_A_A10_G0
PORT_A_A14_G4
PORT_A_A15_G5
PORT_A_A16_G6
PORT_A_A17_G7
PORT_A_A19_G9
PORT_A_A20_R0
PORT_A_A21_R1
PORT_A_A18_G8
PORT_A_A25_R5
PORT_A_A24_R4
PORT_A_A23_R3
PORT_A_A22_R2
PORT_A_A28_R8
PORT_A_A26_R6
PORT_A_A27_R7
PORT_A_A29_R9
GND_1
DRO4
GND_1
PORT_A_CLKA1
PCLKOUT
DGO3
GND_1
GND_1
GND_1
PORT_A_CLKA1
DGO0_AR
DGO1_AR
DGO5_AR
DGO6_AR
DGO7_AR
DBO6_AR
PORT_A_A13_G3
DBO7_AR
PORT_A_A8_B8
DGO8_AR
PORT_A_A9_B9
DGO9_AR
DRO2_AR
DRO3_AR
PORT_A_A3_B3
DRO4_AR
PORT_A_A20_R0
PORT_A_A5_B5
DRO7_AR
PORT_A_A21_R1
DRO0_AR
PORT_A_A6_B6
PORT_A_A25_R5
PORT_A_A22_R2
DRO8_AR
PORT_A_A26_R6
DRO1_AR
PORT_A_HSYNC
PORT_A_A23_R3
DRO9_AR
PORT_A_A27_R7
DRO6_AR
PORT_A_VSYNC
PORT_A_A24_R4
DBO0_AR
DGO4_AR
PORT_A_A7_B7
DRO5_AR
PORT_A_A2_B2
DBO1_AR
PORT_A_A18_G8
DHS_OUT_AR
PORT_A_A19_G9
DVS_OUT_AR
DBO2_AR
DBO3_AR
DGO2_AR
PCLKOUT_AR
DBO4_AR
PORT_A_A16_G6
DGO3_AR
PORT_A_A10_G0
DBO5_AR
PORT_A_A17_G7
PORT_A_A28_R8
DBO8_AR
PORT_A_A11_G1
PORT_A_A0_B0
PORT_A_A29_R9
PORT_A_A12_G2
DBO9_AR
PORT_A_A1_B1
PORT_A_A14_G4
PORT_A_A15_G5
DBO1_AR
DBO0_AR
PCLKOUT_AR
DGO1_AR
DGO0_AR
DRO1_AR
DRO0_AR
DBO9_AR
DBO8_AR
DGO9_AR
DEN_OUT_AR
DRO8_AR
DVS_OUT_AR
DHS_OUT_AR
DBO7_AR
DBO6_AR
DBO5_AR
DBO4_AR
DGO7_AR
DGO6_AR
DGO3_AR
DGO2_AR
DRO7_AR
DRO6_AR
DRO5_AR
DRO4_AR
DRO2_AR
DRO3_AR
DBO3_AR
DBO2_AR
DGO5_AR
PORT_A_A4_B4
DEN_OUT_AR
PORT_A_DE
DVS_OUT
DBO4
DHS_OUT_AR
DBO8
DGO9
DGO4_AR
DBO8_AR
DBO5_AR
DBO5
DGO9_AR
DBO2
DGO3
DGO7_AR
DGO3_AR
DRO6
DVS_OUT_AR
DRO8
DRO7
DHS_OUT
DBO9
DBO4_AR
DBO6_AR
DGO5_AR
DBO2_AR
DRO8_AR
DBO7_AR
DRO4
DRO9_AR
DRO9
DBO9_AR
DGO8_AR
DGO6_AR
DGO4
DBO6
DRO4_AR
DBO7
DGO5
DGO6
DBO3
DGO7
DRO6_AR
DGO8
DBO3_AR
DRO7_AR
DGO8_AR
DRO9_AR
DRO5
DRO5_AR
DGO2
DRO3
DRO2
DEN_OUT
DGO2_AR
DRO3_AR
DRO2_AR
DEN_OUT_AR
DGO4_AR
GND_1
GND_1
TO PANEL
FPGA WINGMAN
GNDA_PLL2
GNDA_PLL1
GND_PLL
LVDS GND
PLACE AS CLOSE AS POSSIBLE
TO PIN 15
PLACE AS CLOSE AS POSSIBLE
TO PIN 27
TO IC5002
PLACE AS CLOSE AS POSSIBLE
GND = BYP
VCC=NORMAL
Imax = 2A
Imax = 2A
Imax = 455mA
Imax = 455mA
ADD CAPACITOR CLOSE VIAS PORT_A LINES (EMC)
6A/13
BC
BC.SE1A
COMPONENTS MARKED AS XX REFER TO PARTS LIST, WILL ONLY BE LISTED IF FITTED
6C/13
BC
6D/13
BC
6B/13
BC
BC.SE1A
BC.SE1A
BC.SE1A
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