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– 4 –
1.3.3
I/O Interface Specification
(1) I/O Signal
No.
Item
Signal Name
Number
of
signals
I/O
Form
Content of definition
Video Signal
Timing Signal
Timing Signal
RA-
RA+
RB-
RB+
RC-
RC+
RD-
RD+
RE-
RE+
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Input
LVDS
Differential
Differential serial data signal.
Input video and timing signals after
differential serial conversion using a
dedicated transceiver.
The serial data signal is transmitted
seven times faster than the base
signal．
Input video and timing signals after
differential serial conversion using a
dedicated transceiver.
The serial data signal is transmitted
seven times faster than the base
signal．
Clock
RXCLKIN-
RXCLKIN+
1
1
1
Input
LVDS
Differential
Differential clock signal.
Input the clock signal after
differential conversion using a
dedicated transceiver.
The clock signal is transmitted at
the same speed as the base signal.
Input the clock signal after
differential conversion using a
dedicated transceiver.
The clock signal is transmitted at
the same speed as the base signal.
1
Di
sp
la
y d
a
ta
Power down
Signal
Signal
PDWN 1 Input
LVTTL
Low :LVDS receiver outputs are all
“L”.
High: Input signals are active.
“L”.
High: Input signals are active.
SDA 1 I/O
Communication
SCL 1
I/O
LVTTL
(I
2
C)
I
2
C bus serial data communication
signal.
Communication with the control
MPU of this product is enabled.
Communication with the control
MPU of this product is enabled.
CPUGO 1 Input
LVTTL
Low power consumption mode of
the control MPU of this product is
released.
the control MPU of this product is
released.
PDPGO 1 Input
LVTTL
“High”: This product is started.
(CPUGO=“High” Effective)
(CPUGO=“High” Effective)
2
M
P
U
C
o
mmunication / C
ontrol
Control
IRQ 1
Output
LVTTL
It changes into "Low"
→ "High"
when this product enters the
undermentioned state.
1. Vcc/Va/Vs output decrease
2. Circuit abnormality detection
undermentioned state.
1. Vcc/Va/Vs output decrease
2. Circuit abnormality detection
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