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~ N Board Schematic Diagram [ Digital Terrestrial Signal Decoder ] Page 2/8 ~
+3V3D
1k
R3238
RDATA[0-15]
10k
R3249
39
R3248
10k
R3250
ATX
0.1
C3214
0.1
C3217
13.5MHz
X3200
PWMOUT
CLK27M
25V
0.1
C3208
25V
0.1
C3209
0.1
C3221
0.1
C3223
+2V5D
DADD[0-12]
DBA0,DBA1,DCASB,DCLK,DCLKB,DCSB,DQM0,DQM1,DQS0,DQS1,DRASB,DVREF,DWEB
DQ[0-15]
0.1
C3222
0.1
C3220
EVCLK
EIVHS
8
7
6
5
4
3
2
1
FS6128-04
IC3204
XIN
Vdd
XTUNE
Vss
CLK
NC
Vss
XOUT
NAND_ALE,NAND_CLE,NAND_RBB,NAND_SEB
+3V3D
+3V3D
+3V3D
XX
R3207
XX
R3208
1k
R3216
1k
R3224
1k
R3232
XX
R3237
1k
R3236
1k
R3230
1k
R3229
XX
R3223
XX
R3231
1k
R3222
XX
R3235
XX
R3228
XX
R3221
XX
R3219
1k
R3206
XX
R3209
XX
R3217
1k
R3218
XX
R3225
XX
R3226
1k
R3227
XX
R3233
1k
R3234
SHT2_+3.3V_STRAP
470
R3251
XX
R3252
0
R3253
FOEB
FCSB1
FCSB0
FWEB
25V
0.1
C3205
0uH
L3202
25V
0.1
C3225
0uH
L3206
0uH
L3204
1000p
C3218
C3227
XX
L3203
XX
C3207
XX
C3210
XX
R3240 XX
R3241
XX
R3245
XX
R3246
XX
R3247
XX
C3212
XX
R3244
XX
R3243
XX
0
R3257
XX
R3256
XX
R3210
XX
R3258
16V
4.7
C3206
16V
4.7
C3204
1/10W
1k
R3262
XX
R3263
1/10W
100
R3260
1/10W
100
R3261
R3264
XX
FWEB
nCE_NAND
nCE_NAND
nSE_NAND
nSE_NAND
FOEB
C3228
0.1
C3229
0.1
GND
1000p
C3230
1p
C3213
1p
C3215
2.2k
R3211
2.2k
R3213
2.2k
R3212
2.2k
R3214
2.2k
R3220
XX
R3215
48
9
53
56
1
49
50
51
2
55
54
52
345678
47
10
46
45
44
43
42
11
12
13
14
15
41
40
39
38
37
36
35
16
17
18
19
20
21
22
34
33
23
24
32
25
31
30
29
26
27
28
57
58
59
60
61
62
63
64
65
66
IC3205
EDD1216AATA-6B-E
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10
A0
A1
A2
A3
A3
DQ15
VSS
A4
A5
A6
A7
A8
A9
A11
A12
NC
CKE
CLK
CLK
UDM
VSS
VREF
NC
UDQS
VSSQ
NC
DQ8
VDDQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VDDQ
DQ13
DQ14
VSSQ
VSS
VDD
R3265
0
R3266 XX
R3267
1k
25V
0.1
C3231
nNAND_WP
nNAND_WP
1
44
43
42
41
40
39
38
234567
37
36
35
8
91
0
32
31
30
29
28
27
13
14
15
16
17
18
19
26
25
24
23
20
21
22
IC3207
Vss
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O1
I/O2
I/O3
I/O4
Vss
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
RY/BY
RE
CE
Vcc
VDO[0-7],EOVVS,EOVHS,VCK
6.3V
100
C3224
16V
4.7
C3232
C3211
XX
R3242 XX
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IC3203
L VDD
SELECT
VCO
FINA
FINB
PFD OUT
L GND
NC
PFD INH
VCO INH
VCO GND
VCO IN
R BIAS
VDD
48
43
6
5
46
4
3
2
1
47
45
44
42
41
37
38
39
40
12
10
11
9
8
7
36
31
32
33
34
35
18
17
16
15
14
13
30
29
28
27
26
25
24
23
22
21
20
19
IC3206
XX
NC
NC
NC
NC
NC
SE
RB
FOE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O1
I/O2
IO/3
IO/4
NC
NC
NC
VSS
VCC
NC
NC
NC
IO/5
IO/6
IO/7
IO/8
NC
NC
NC
NC
0.1
C3219
RDATA[10]
RDATA[2]
RDATA[5]
RDATA[4]
RDATA[12]
RDATA[15]
RDATA[13]
RDATA[0]
RDATA[1]
RDATA[6]
RDATA[9]
ATX
RDATA[8]
RDATA[11]
RDATA[14]
RDATA[7]
NAND_ALE
NAND_CLE
DADD[6]
DQM0
DQ[4]
DQS0
DADD[5]
DQ[14]
DQ[10]
DQ[3]
DQ[2]
DQ[0]
DRASB
DQ[15]
DVREF
DQ[1]
DQM1
DADD[10]
DQS1
DADD[11]
DADD[3]
DQ[11]
DADD[0]
DQ[8]
DQ[7]
DCASB
DQ[6]
DADD[12]
DADD[1]
DQ[12]
DADD[9]
DQ[9]
DBA1
DQ[13]
DADD[2]
DADD[8]
DBA0
DADD[4]
DCSB
DWEB
DADD[7]
DQ[5]
CLK_PSU_FILT
RDATA[0]
RDATA[1]
RDATA[3]
RDATA[4]
RDATA[5]
RDATA[7]
RDATA[6]
RDATA[2]
NAND_SEB
DCLK
DCLKB
RDATA[3]
RDATA[0]
RDATA[1]
RDATA[2]
RDATA[3]
RDATA[4]
RDATA[5]
RDATA[6]
RDATA[7]
NAND_RBB
NAND_CLE
NAND_ALE
NAND_RBB
SIGN10540
DVREF
EOVVS
DDR SDRAM
STRAP PINS
27MHz CLOCK GENERATION
NAND FLASH
H_PLL
PLACE THESE CAPACITORS CLOSE TO IC PINS.
PLL
PLACE R3258 CLOSE TO IC3205
BIG ENDIAN
FULL MERGE
FULL MERGE
FIXED (DEBUG)
166MHz MAIN CPU CLOCK
166MHz MAIN CPU CLOCK
EDINT DISABLED
132.75 MHz DDR CLK
132.75 MHz DDR CLK
132.75 MHz DDR CLK
ROM BUS BIG ENDIAN
EXTERNAL BOOT
8 BIT MODE
NAND BOOT FCSB1
RESERVED
RESERVED
RESERVED
BOOT FROM DaMON FLASH
RDATA[0] = 1 -> MIPS32 IS BIG-ENDIAN
RDATA[2:1] = 10 -> FULL MERGE MODE
RDATA[3] = 0 -> FIXED (DEBUG)
RDATA[5:4] = 01 -> VRCLK = 166 MHz
RDATA[6] = 0 -> EDINT DISABLED
RDATA[9:7] = 011 -> MEMORY MCLK = 133 MHz
RDATA[10] = 1 -> ROM IS BIG ENDIAN
RDATA[11] = 0 -> NAND FLASH IS 256Mb OR LESS
RDATA[12] = 1 -> USE INTERNAL BOOT ROM
RDATA[15:13] = 000 -> USE NAND FLASH
ATX (SPDIF) = 1 -> USE FCS1B FOR NAND BOOT
RDATA[2:1] = 10 -> FULL MERGE MODE
RDATA[3] = 0 -> FIXED (DEBUG)
RDATA[5:4] = 01 -> VRCLK = 166 MHz
RDATA[6] = 0 -> EDINT DISABLED
RDATA[9:7] = 011 -> MEMORY MCLK = 133 MHz
RDATA[10] = 1 -> ROM IS BIG ENDIAN
RDATA[11] = 0 -> NAND FLASH IS 256Mb OR LESS
RDATA[12] = 1 -> USE INTERNAL BOOT ROM
RDATA[15:13] = 000 -> USE NAND FLASH
ATX (SPDIF) = 1 -> USE FCS1B FOR NAND BOOT
N
2/8
N..-32DX51AUS
TC58V64BTG(YBDL)-BL1-01AUS
XX
NAND FLASH MEMORY
DDR SDRAM MEMORY
27MHZ CLOCK GENERATING IC
COMPONENTS MARKED AS XX ARE NOT FITTED ON THIS MODEL
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