Read Sony DPP-M55 (serv.man2) Service Manual online
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2. Circuit
(1) Power supply circuit
Circuit operations are performed with the following voltages.
• +22V
Voltage for the thermal head, PLATEN motor (M904), and motor driver (IC900).
The head voltage is adjusted by VR201 when the thermal head has been replaced. When the head voltage changes, the
The head voltage is adjusted by VR201 when the thermal head has been replaced. When the head voltage changes, the
color darkness also changes.
• +7V
Voltage for the motor driver (IC900) and auto feeder motor.
Voltage output is controlled by the switching output of Pin !¡ according to the voltage input to Pin 1 of IC203 as the
Voltage output is controlled by the switching output of Pin !¡ according to the voltage input to Pin 1 of IC203 as the
switching regulator controller of the board (J/US:SR784, AEP:SR786).
• D+5V
Voltage for the digital circuit regulated from +7V by IC110 of the DK-31 board. Voltage for most of the digital signal
processing operations of the system controller, mechanism controller, DRAM, etc.
• +5V
Voltage for the FAN motor regulated by IC202 of the board (J/US:SR784, AEP:SR786).
(Repair Tips) Checking of power supply board
Each voltage (+22V, +7V, D+5V, +5V) can be output by removing only the power supply board.
(2) Communication circuit
(i)
IrDA
The RXD signal input from the IrDA terminal (IC650) is decoded by the IrDA interface (IC507) and recorded in the 4
Mbit DRAM (IC506) by the address bus (A0 to A3) and data bus (D0 to D7) via the microprocessor (IC503).
The IrDA communication clock is output by X500 (48 MHz) and IC500.
(ii) Centronics parallel
The image data signal from jack 1 is latched by the flip-flop (IC118) and recorded in the 4 Mbit DRAM (IC506) via the
microprocessor (IC503).
The other control signals are waveform-shaped by the buffer (IC123), NOR gate (IC101), and gate (IC102), and input/
output together with the system controller, etc.
(iii) MAC SERIAL
The ±5Vp-p input data and clock are voltage level shifted by IC103 and input to the system controller (IC503).
(3) Printing circuit
The image data input by each route is decoded by the system controller (IC503), and recorded in the 4 Mbit DRAM
(IC506) by the address bus and data bus.
The data recorded in the 4 Mbit DRAM is read to the mechanism controller (IC505) and output to the thermal head from
PDT0 (Pin @£) and PDT1 (Pin @™).
The image data is output in order from yellow, magenta, and cyan.
W If printing cannot be carried out, check if the flexible board is connected properly.
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