Read Sony DPP-EX50 (serv.man2) Service Manual online
5-5
DPP-EX50 V2
IC
157
160
165
170
175
180
185
190
195
200
205
208
CPU INTERFACE
—TOP VIEW—
104
100
95
90
85
80
75
70
65
60
55
53
156 155
150
145
140
135
130
125
120
115
110
105
1
5
10
15
20
25
30
35
40
45
50
52
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
STM OUT 5
STM OUT 6
DCM OUT 0
DCM OUT 1
DCM OUT 2
DCM OUT 3
V
CC
E
GND
DSP D 0
DCM OUT 4
DCM OUT 5
DCM OUT 6
CPU WAIT
DSP D 1
V
CC
I
DCM OUT 7
PORT 0
PORT 1
DSP D 2
PORT 2
GND
PORT 3
PORT 4
DSP D 3
PORT 5
PORT 6
PORT 7
PORT 8
DSP D 4
PORT 9
PORT 10
GND
PORT 11
DSP D 5
PORT 12
PORT 13
PORT 14
V
CC
E
DSP D 6
CA A 0
PORT 15
XTST
V
CC
I
DSP D 7
GND
CLK 1
CPU SEL
RESET
CS A 1
CS A 2
CPU RD
IVPD
CLK 0
MST
CPU WE 0
CPU WE 1
CPU WE 1
XSM
CPU BS
CPU CS
CPU CS
SMCK
DSP D 8
CPU A 15
CPU A 14
CPU A 13
CPU A 12
DSP D 9
CPU A 11
CPU A 10
CPU A 9
CPU A 8
DSP D 10
V
CC
I
GND
CPU A 7
CPU A 6
DSP D 11
CPU A 5
CPU A 4
CPU A 3
CPU A 2
DSP D 12
CPU A 1
CPU A 0
GND
V
CC
E
DSP D 13
CPU IRL 0
CPU IRL 1
CPU IRL 2
CPU IRL 3
CPU IRL 1
CPU IRL 2
CPU IRL 3
DSP D 14
CS OUT 0
CS OUT 1
CS OUT 2
CS OUT 3
NC
V
CC
E
CPU D 0
CPU D 1
CPU D 2
CPU D 3
GND
CPU D 4
CPU D 5
I/O
I/O
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
—
—
I/O
I/O
I
I/O
—
I/O
I/O
I
I/O
I/O
I/O
I
I
I/O
—
—
O
—
O
O
O
—
—
O
O
O
O
—
—
—
O
O
O
O
O
O
CPU D 6
CPU D 7
V
CC
E
CPU D 8
CPU D 9
CPU D 10
CPU D 11
GND
NC
CPU D 12
CPU D 13
CPU D 14
CPU D 15
NC
V
CC
I
V
CC
E
PORT 16
PORT 17
DSP D 15
PORT 18
GND
PORT 19
PORT 20
DSP WE
PORT 21
PORT 22
PORT 23
TEST IN
DSP CS
PRINT PLS
V
CC
E
GND
HED D 0
NC
HED D 1
HED D 2
HED D 3
V
CC
E
NC
HED CK
HED LATCH
HED STRB
HED D 4
NC
GND
V
CC
E
HED D 5
HED D 6
HED D 7
HED D 8
HED D 9
HED D 10
O
O
O
O
O
O
O
O
—
—
—
O
—
—
—
—
O
I
—
O
I
O
I
—
—
—
O
I
—
I
O
I
O
—
I
O
—
—
—
—
O
O
—
—
—
O
—
—
O
O
O
O
HED D 11
HED D 12
HED D 13
HED D 14
HED D 15
HED D 16
HED D 17
HED D 18
NC
V
CC
I
V
CC
E
HED D 19
GND
NC
A.GND
A.V
CC
SVR 0
SADIN 0
NC
SVR 1
SADIN 1
SVR 2
SADIN 2
NC
A.V
CC
A.GND
SVR 3
SADIN 3
NC
SADIN 4
SVR 4
SADIN 5
SVR 5
NC
HADIN
HVR
A.GND
A.V
CC
NC
A.GND
DAO 0
DAO 1
A.V
CC
NC
GND
STM OUT 0
V
CC
I
V
CC
E
STM OUT 1
STM OUT 2
STM OUT 3
STM OUT 4
O
O
O
O
O
O
—
—
I
O
O
O
O
I
—
O
I/O
I/O
I
I/O
—
I/O
I/O
I
I/O
I/O
I/O
I/O
I
I/O
I/O
—
I/O
I
I/O
I/O
I/O
—
I
I
I/O
I
—
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
—
I
I
I
I
I
I
I
I
I
I
—
—
I
O
O
O
O
I
O
O
O
O
—
—
I/O
I/O
I/O
I/O
—
I/O
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
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152
153
154
155
156
157
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160
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162
163
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200
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208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
CS OUT 0
CS OUT 1
CS OUT 2
CS OUT 3
CPU SEL
92
93
94
95
47
CPU
INTERFACE
CPU
CLK0
CLK1
RESET
53
46
48
DAO 0
DAO 1
197
198
CLOCK
RESET
CONT
DSP
HEAD CONT
TEST
CIRCUIT
CPU IRL 0
CPU IRL 1
CPU IRL 2
CPU IRL 3
87
88
89
90
D/A
8-BIT
A/D
10-BIT
1 MHz
x
2
x
6
DPRAM
128 WORDS
x
36-BIT
x
10
MECHANICAL CONT
DPRAM
128 WORDS
x
16-BIT
x
1
DPRAM
512 WORDS
x
9-BIT
x
3
CPU ADDRESS/DATA BUS
DAC
CONT
IRQ
CONT
A/D
10-BIT
1 MHz
HED D 0 - HED D 19
HED CK
HED STRB
HED LATCH
HED LATCH
PRINT PLS
CS A 0 - CS A 2,
CPU A 0 - CPU A15,
CPU D 0 - CPU D15,
CPU A 0 - CPU A15,
CPU D 0 - CPU D15,
CPU CS
,
CPU RD
,
CPU WE 0
,
CPU WE 1
,
CPU BS
,
CPU WAIT
DSP CS
,
DSP WE
,
DSP D 0 - DSP D 15
20
TEST IN
132
144
146
145
134
HADIN
HVR
191
192
DCM OUT 0 - DCM OUT 7
STM OUT 0 - STM OUT 6
PORT 0 - PORT 23
SADIN 0 - SADIN 5
SVR 0 - SVR 5
8
7
24
6
6
CXD9182R (SONY)
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