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4-9
HDR-SR11/SR11E/SR12/SR12E_L3
VC-516 (5/22)
D _ 1 . 8 V
C 1 6 0 2
0 . 1 u
B
1 0 V
C 1 6 0 4
0 . 1 u
B
1 0 V
C 1 6 0 5
0 . 1 u
B
1 0 V
C 1 6 0 1
4 . 7 u
B
6 . 3 V
C 1 6 0 3
0 . 1 u
B
1 0 V
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 6
R E G _ G N D
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 1 0
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 0
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 2
I C _ 1 3 0 1 _ D D R 2 _ D C L K N
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 9
I C _ 1 3 0 1 _ D D R 2 _ X C S _ 0
I C _ 1 3 0 1 _ D D R 2 _ X C A S
I C _ 1 3 0 1 _ D D R 2 _ C K E 1
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 1 1
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 4
R E G _ G N D
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 1 2
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 5
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 1 3
I C _ 1 3 0 1 _ D D R 2 _ X R A S
I C _ 1 3 0 1 _ D D R 2 _ C L K
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 1
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 3
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 7
I C _ 1 3 0 1 _ D D R 2 _ A D D R _ 8
I C _ 1 3 0 1 _ D D R 2 _ B A _ 1
D _ 1 . 8 V
I C _ 1 3 0 1 _ D D R 2 _ B A _ 0
I C _ 1 3 0 1 _ D D R 2 _ X W E
I C _ 1 3 0 1 _ D D R 2 _ D Q S _ 1
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 1
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 0
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 1
IC_1301_DDR2_DQS_0
I C _ 1 3 0 1 _ D D R 2 _ D Q M _ 1
IC_1301_DDR2_DATA_1
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 5
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 4
IC_1301_DDR2_DATA_29
IC_1301_DDR2_DATA_4
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 8
IC_1301_DDR2_DATA_5
I C _ 1 3 0 1 _ D D R 2 _ D Q S _ 2
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 5
IC_1301_DDR2_DATA_31
IC_1301_DDR2_DATA_3
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 7
IC_1301_DDR2_DATA_2
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 3
IC_1301_DDR2_DATA_0
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 4
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 2
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 8
IC_1301_DDR2_DATA_27
IC_1301_DDR2_DATA_30
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 2
IC_1301_DDR2_DATA_28
IC_1301_DDR2_DQS_3
I C _ 1 3 0 1 _ D D R 2 _ D Q M _ 0
I C _ 1 3 0 1 _ D D R 2 _ D Q M _ 2
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 0
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 6
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 1 9
IC_1301_DDR2_DATA_7
IC_1301_DDR2_DATA_26
IC_1301_DDR2_DQM_3
IC_1301_DDR2_DATA_6
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 2 3
I C _ 1 3 0 1 _ D D R 2 _ D A T A _ 9
I C 1 6 0 1
K 4 X 5 6 3 2 3 P I - 8 G C 6 T
R 1
VSS
F 9
VSS
A 1
VSS
R 3
VSSQ
P 9
VSSQ
N 1
VSSQ
M 9
VSSQ
L 1
VSSQ
E 1
VSSQ
D 9
VSSQ
C 1
VSSQ
B 9
VSSQ
A 3
VSSQ
R 8
DQ0
P 7
DQ1
P 8
DQ2
N 7
DQ3
N 8
DQ4
M 7
DQ5
M 8
DQ6
L 7
DQ7
L 8
DQS0
K8
D M 0
L3
D Q 8
M2
D Q 9
M3
D Q 1 0
N2
D Q 1 1
N3
D Q 1 2
P2
D Q 1 3
P3
D Q 1 4
R2
D Q 1 5
L2
D Q S 1
K2
D M 1
A8
D Q 1 6
B7
D Q 1 7
B8
D Q 1 8
C7
D Q 1 9
C8
D Q 2 0
D7
D Q 2 1
D8
D Q 2 2
E7
D Q 2 3
E8
D Q S 2
F8
D M 2
E3
D Q 2 4
D2
D Q 2 5
D 3
DQ26
C 2
DQ27
C 3
DQ28
B 2
DQ29
B 3
DQ30
A 2
DQ31
E 2
DQS3
F 2
DM3
A 7
VDDQ
B 1
VDDQ
C 9
VDDQ
D 1
VDDQ
E 9
VDDQ
L 9
VDDQ
M 1
VDDQ
N 9
VDDQ
P 1
VDDQ
R 7
VDDQ
A 9
VDD
F 1
VDD
R 9
VDD
F 3
A13
H3
A 1 2
H2
A 1 1
J7
A 1 0
H1
A 9
J3
A 8
J2
A 7
J1
A 6
K3
A 5
K1
A 4
K9
A 3
K7
A 2
J9
A 1
J8
A 0
H9
B A 1
H8
B A 0
G9
R A S #
G8
C A S #
G7
W E #
H7
C S #
G1
C K E
G2
C K
G3
C K #
F7
N C
R 1 6 0 2
0
R 1 6 0 1
X X
0 8
C
A
B
D
E
D
3
B
F
2
C
1
8
6
A
5
7
F
4
E
M O B I L E D D R S D R A M
X X M A R K : N O M O U N T
M O B I L E D D R S D R A M
V C - 5 1 6 B O A R D ( 5 / 2 2 )
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