Read Sony DCR-PC350 / DCR-PC350E Service Manual online
DCR-PC350/PC350E
4-2. SCHEMATIC DIAGRAMS
VC-370 BOARD SIDE A
VC-370 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-370 BOARD SIDE A
VC-370 BOARD SIDE B
4-43
4-44
VC-370 (7/17)
:Voltage measurement of the CSP IC
and the Transistors with mark, is
not possible.
not possible.
2.8
1.5
1.5
2.8
1.5
2.8
1.5
1.4
2.8
NO MARK:REC/PB MODE
RYO2_DEFLD
RYI2_DE2
CL2304
0.1u
B
C2322
0.1u
C2309
THCRQ_FHDI
LBUS3
RECCK
RYI1_DE1
RECA2
RYO3_SGOUT
REG_GND
10uH
L2308
RYI0_DE0
10uH
L2301
10uH
L2303
4.7u
B
C2312
VLAT_IN_FYO1
LBUS0
CL2311
0.1u
C2305
0.1u
C2310
CL2308
0.1u
C2306
TRRV
XX
C2323
1k
R2301
RFIN
RCO1_EDVD
DRP
TRRT
A_1.5V
VCK
RECDT
0uH
FB2302
FRRV
FS_EDGE_REF
0.1u
B
C2321
SFD_LRCK
4.7u
B
C2324
CL2309
RYO1_DEVD
DXXA08
4.7u
B
C2311
XACC
CL2316
THYRQ_FVDI
DXXA09
D27A03
RCO3_FRMREF
WRX
0
R2318
SWP
SFD_BCK
CL2320
10uH
L2302
ALE
CL2323
TRCKO
D24A00
CL2303
XCS_IC2201
XX
L2310
D30A06
FRAT_REFO
XX
B
C2302
CL2312
VSP_SI
4.7u
B
C2301
XENA
CL2313
LBUS1
RCO0_EDHD
RCO2_EDFLD
LBUS2
D_2.8V
RCI2_DE6
HYI_PLL27IN
XX
L2309
RYO0_DEHD
VSP_SO
RCI1_DE5
0
R2314
D26A02
XSYS_RST
4.7u
B
C2318
CL2322
RDX
RCI0_DE4
XX
C2327
D31A07
10uH
L2304
ATF_LATCH
D_1.5V
0.1u
B
C2325
HCI_FYI0
VLAT_SYNC_FCI
0.1u
C2308
10uH
L2307
FRL
XVSP_SCK
TFS_FCO
RYI3_DE3
HCO_FYI1
DSCK_VM
FLAT_SYNC_FYO0
D25A01
A_2.8V
RECA1
0.1u
C2320
ADATAOUT1
ADATAIN1
XX
C2326
0.1u
C2307
10uH
L2306
ADATAOUT0
CL2302
MFLG_QRST
0.1u
C2303
ADATAIN0
D28A04
CL2310
0
R2312
RCI3_DE7
XX
C2319
CL2321
0.1u
C2304
D29A05
0
R2311
FCLR
XX
R2321
CL2301
DIR
XCS_IC2301
HYO_SLGATE
CL2317
XRST_VTR
XX
R2322
RP_2.8V
R2326
XX
UPD15002AFC-DN2-E2-A
IC2301
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
44
52
43
51
42
50
41
49
40
48
39
47
38
46
37
45
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
SWP
VSP_SO
TRRV
FRRV
TRRT
XVSP_SCK
1
A
R2310
0
HYO_SLGATE
RYO0_DEHD
RYO1_DEVD
RYO2_DEFLD
RYO3_SGOUT
HCO_FYI1
RCO0_EDHD
RCO1_EDVD
RCO2_EDFLD
RCO3_FRMREF
HYI_PLL27IN
RYI0_DE0
RYI1_DE1
RYI2_DE2
RYI3_DE3
HCI_FYI0
RCI0_DE4
RCI1_DE5
RCI2_DE6
RCI3_DE7
MFLG_QRST
TFS_FCO
THYRQ_FVDI
THCRQ_FHDI
VLAT_SYNC_FCI
FLAT_SYNC_FYO0
VLAT_IN_FYO1
DSCK_VM
FS_EDGE_REF
FRAT_REFO
SFD_BCK
SFD_LRCK
ADATAIN0
ADATAIN1
ADATAOUT0
ADATAOUT1
XSYS_RST
XCS_IC2301
SWP
XCS_IC2201
ALE
WRX
D31A07
D30A06
D29A05
D28A04
D27A03
D26A02
D25A01
D24A00
FRRV
DRP
TRRT
TRRV
RDX
XENA
DIR
FCLR
FRL
LBUS3
LBUS2
LBUS1
LBUS0
RECA1
RECA2
RECDT
ATF_LATCH
TRCKO
RECCK
RFIN
XACC
HYI_PLL27IN
RYI0_DE0
RYI2_DE2
FLAT_SYNC_FYO0
MFLG_QRST
SFD_BCK
TRCKO
FCLR
XENA
XVSP_SCK
D25A01
D31A07
RDX
TRRV
TRRT
TFS_FCO
RECA2
RECA1
DIR
FRL
D24A00
D28A04
ALE
FRRV
DRP
SWP
RCO0_EDHD
RCO2_EDFLD
R
Y
I1_DE1
R
Y
I3_DE3
HCI_FYI0
VLA
T_SYNC_FCI
VLA
T_IN_FYO1
SFD_LRCK
RYO2_DEFLD
RCO1_EDVD
RCO3_FRMREF
RCI0_DE4
RCI2_DE6
RCI3_DE7
ADATAOUT1
ADATAIN1
FS_EDGE_REF
RFIN
LBUS0
LBUS2
XACC
D26A02
D29A05
WRX
DXXA08
A
T
F_LA
TCH
XCS_IC2301
R
YO3_SGOUT
HYO_SLGA
TE
HCO_FYI1
RCI1_DE5
ADA
T
AOUT0
A
D
ATA
IN
0
FRA
T_REFO
LBUS1
LBUS3
XCS_IC2201
D27A03
D30A06
DXXA09
VSP_SO
XSYS_RST
DXXA09
DXXA08
DSCK_VM
RECCK
RECDT
R
YO1_DEVD
THCRQ_FHDI
RYO0_DEHD
XRST_VTR
XRST_VTR
THYRQ_FVDI
XVSP_SCK
VSP_SO
SWP
VSP_SO
TRRT
TRRV
FRRV
XVSP_SCK
AMC
MSSCK
AGND
N.C.
IOVDD2(3.0V)
INTV1(1.5V)
N.C.
IOVDD1(3.0V)
IOGND1(3V)
INTV2(1.5V)
HYO
YO0
YO2
TICK
IOGND3(3.0V)
SMC
FLAT_SYNC
TMFLG
INTG3(1.5V)
BCK
INTV3(1.5V)
MDQ1
MDQ5
IOGND2(3.0V)
PBCK
ADDT0
PLLSW
INTV4(1.5V)
IOVDD3(3.0V)
TRST
DICK
INTV5(1.5V)
N.C.
DICO_DVDD
VRT
ADGND
OSCIN
OVDD
RECCKO
PLLSVDD
INTG5(1.5V)
RECDT
IOGND5(3.0V)
RECA2
RECA1
TEST
INTG6(1.5V)
LDIR
INTV6(1.5V)
FRL
MCDA0
MCDA4
INTG7(1.5V)
ALE
FRRV
DRP
SWP
IOGND6(3.0V)
N.C.
XRST
THCRQ
INTG2(1.5V)
CI0
CI2
YO1
YO3
IOVDD4(3.0V)
HCO
VLA
T_SYNC
VLA
T_IN
LRCK
MDQ0
MDQ2
MDQ6
INTG4(1.5V)
ADDT3
N.C.
PLLMSK
IOGND7(3.0V)
INTG8(1.5V)
N.C.
DGND
ADVDD
VRB
OSCOUT
PCOR
PLLRVDD
IOGND4(3.0V)
PLLSGND
IOVDD6(3.0V)
CCDMODE0
TEST1
CCDMODE1
TRCKO
FCLR
XENA
MCDA1
INTV7(1.5V)
MCDA7
RDX
TRRV
TRRT
INTG1(1.5V)
TFS
YI0
YI2
CI1
CI3
CO0
CO2
CO3
ADATAOUT1
ADATAIN1
FS_EDGE_REF
MDQ3
MDQ7
ADDT5
ADDT2
DICO_AVDD
RFIN
OSCVDD
OGND
PLLRGND
TGCK
INTV8(1.5V)
N.C.
TEST2
BUNRI
LBUS0
LBUS2
XACC
MCDA2
MCDA5
WRX
MCHA0
A
TFSMPL
MSO2MC
MSCSR
THYRQ
YI1
YI3
HYI
HCI
CO1
ADA
T
AOUT0
ADA
T
A
IN0
FRA
T_REFO
MDQ4
MDQ8
ADDT4
ADDT1
N.C.
VRC
N.C.
OSCGND
IOVDD5(3.0V)
INTG9(1.5V)
SPCKO
TEST3
LBUS1
LBUS3
MCCE
MCDA3
MCDA6
SCWIN
MCHA1
MSI2ROTA
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
IC2301
DV SIGNAL PROCESS
DV/RF SIGNAL PROCESS(R BLOCK)
VC-370 BOARD(7/17)
XX MARK:NO MOUNT
16
SIGNAL PATH
SIGNAL
CHROMA
REC
PB
AUDIO
Y
VIDEO SIGNAL
Y/CHROMA
PB
Ref.signal
SIGNAL PATH
REC
REC/PB
10
G
H
5
13
L
6
E
3
8
B
12
D
C
9
2
4
7
J
I
17
16
18
19
F
K
11
15
14
CSP (CHIP SIZE PACKAGE) IC
@04
(11/17,12/17,
16/17)
16/17)
@16
(1/17,3/17,4/17,
6/17,12/17,
13/17,15/17)
6/17,12/17,
13/17,15/17)
(12/17)
@44
@45
(8/17,12/17)
(8/17)
@46
(11/17,12/17.
14/17)
14/17)
@47
(9/17)
@50
(17/17)
@51
@15
(3/17,4/17)
@24
(4/17)
For Schematic Diagram
• Refer to page 4-89 for printed wiring board.
• Refer to page 4-89 for printed wiring board.
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