Read Sony DCR-PC109 / DCR-PC109E Service Manual online
DCR-PC109/PC109E
4-2. SCHEMATIC DIAGRAMS
VC-352 BOARD SIDE A
VC-352 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-352 BOARD SIDE A
VC-352 BOARD SIDE B
4-37
4-38
VC-352 (8/21)
For Schematic Diagram
• Refer to page 4-79 for printed wiring board.
• Refer to page 4-79 for printed wiring board.
:Voltage measurement of the CSP IC
and the Transistors with mark,is
not possible.
and the Transistors with mark,is
not possible.
VSP_SO
D26A02
XACC
L6405
0uH
HCI_FYI0
RCI1_DE5
RCO3_FRMREF
ALE
D29A05
ADATAIN0
VSP_SI
SWP
CL6402
RECCK
MFLG_QRST
XSYS_RST
UPD15002AFC-DN2-E2-A
IC6401
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
44
52
43
51
42
50
41
49
40
48
39
47
38
46
37
45
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
RYI2_DE2
RECA1
VLAT_IN_FYO1
A_2.8V
RYI3_DE3
RCI0_DE4
RYI0_DE0
D30A06
SFD_LRCK
CL6401
HYO_SLGATE
RECA2
ATF_LATCH
HYI_PLL27IN
RYI1_DE1
FRL
XENA
RYO1_DEVD
DSCK_VM
TRRV
TFS_FCO
VCK
HCO_FYI1
REG_GND
RCO0_EDHD
LBUS1
LBUS0
RCO2_EDFLD
ADATAIN1
TRRT
D27A03
THYRQ_FVDI
THCRQ_FHDI
DRP
L6404
10uH
D_2.8V
LBUS2
D31A07
FRRV
FS_EDGE_REF
RP_2.8V
RCI3_DE7
DXXA08
SFD_BCK
D28A04
RECDT
XVSP_SCK
XRST_VTR
D24A00
D_1.5V
ADATAOUT1
B
C6411 4.7u
XCS_IC6301
RYO0_DEHD
RYO3_SGOUT
RDX
DXXA09
RCI2_DE6
LBUS3
A_1.5V
TRCKO
B
C6413
4.7u
D25A01
FRAT_REFO
DIR
RCO1_EDVD
XCS_IC6401
RFIN
RYO2_DEFLD
WRX
FCLR
FLAT_SYNC_FYO0
VLAT_SYNC_FCI
ADATAOUT0
CL6403
CL6404
CL6405
4.7u
B
C6417
0.1u
C6410
0.1u
C6405
0.1u
C6408
0.1u
B
C6409
XX
C6419
R6407
1k
4.7u
B
C6416
0.1u
C6415
0uH
L6406
4.7u
B
C6404
10uH
L6401
C6414
0.1u
XX
R6414
XX
R6416
XX
C6412
R6413
0
0.1u
B
C6421
XX
R6406
XX
C6401
XX
R6411
0.1u
C6406
XX
C6407
4.7u
B
C6418
0uH
FB6401
0.1u
C6420
0.1u
C6403
4.7u
B
C6402
0
R6412
0uH
L6407
0uH
L6402
0.1u
B
C6422
0uH
L6409
0
R6401
CL6406
1
A
RCO2_EDFLD
TFS_FCO
ADATAIN1
D31A07
HYI_PLL27IN
RECDT
FS_EDGE_REF
HCI_FYI0
ADATAOUT0
D24A00
VSP_SO
RCI0_DE4
RECA2
ADATAOUT1
VLA
T_SYNC_FCI
FRRV
RCI1_DE5
SWP
R
YO3_SGOUT
VLA
T_IN_FYO1
DRP
RCI2_DE6
XCS_IC6301
HYO_SLGA
TE
SFD_LRCK
XSYS_RST
TRRT
MFLG_QRST
ADA
T
AOUT0
RCI3_DE7
TRCKO
ALE
HCO_FYI1
VSP_SI
RYO2_DEFLD
TRRV
SFD_BCK
MFLG_QRST
FCLR
WRX
THCRQ_FHDI
RCI1_DE5
VSP_SO
RCO1_EDVD
TRRT
RDX
TFS_FCO
D31A07
XENA
DRP
THYRQ_FVDI
FRA
T_REFO
RECA1
THYRQ_FVDI
SWP
THCRQ_FHDI
XENA
ADA
T
AIN0
XVSP_SCK
RYO1_DEVD
RCO0_EDHD
VLAT_SYNC_FCI
DIR
XSYS_RST
RCO2_EDFLD
FLAT_SYNC_FYO0
FCLR
DXXA09
VSP_SI
R
YI1_DE1
VLAT_IN_FYO1
FRL
HYO_SLGATE
DXXA08
XCS_IC6401
R
YI3_DE3
DSCK_VM
LBUS3
RYO0_DEHD
DSCK_VM
RCO3_FRMREF
R
YO1_DEVD
D30A06
HYI_PLL27IN
RYO0_DEHD
DIR
D29A05
FRL
RECCK
XRST_VTR
RYI0_DE0
ATF_LATCH
LBUS0
D28A04
D24A00
RYI1_DE1
RFIN
LBUS2
D27A03
D28A04
RYI0_DE0
RYI2_DE2
XACC
D26A02
RECCK
ALE
RYI2_DE2
RYI3_DE3
XRST_VTR
D26A02
D25A01
FRRV
FLAT_SYNC_FYO0
XCS_IC6401
HCI_FYI0
RCO3_FRMREF
LBUS1
XVSP_SCK
RYO2_DEFLD
D29A05
RDX
FS_EDGE_REF
LBUS2
RCI0_DE4
LBUS3
RYO3_SGOUT
WRX
TRRV
FRAT_REFO
LBUS1
RCI2_DE6
XCS_IC6301
HCO_FYI1
TRCKO
DXXA08
SFD_BCK
LBUS0
RCI3_DE7
D27A03
RCO0_EDHD
A
TF_LA
TCH
SFD_LRCK
RECA1
ADATAOUT1
D30A06
RCO1_EDVD
ADATAIN0
D25A01
XACC
RECA2
ADATAIN1
DXXA09
RFIN
RECDT
LBUS3
MCDA7
ADGND
VLA
T_IN
OSCGND
MDQ5
IOGND3(3.0V)
INTV7(1.5V)
MCDA1
VLA
T_SYNC
INTG7(1.5V)
MDQ1
TICK
ALE
THCRQ
XENA
N.C.
YO2
FCLR
INTV3(1.5V)
VRC
FRRV
TRCKO
YO0
BCK
HCI
CCDMODE1
SWP
HYO
TFS
INTG3(1.5V)
LBUS1
HYI
TEST1
IOGND7(3.0V)
AGND
FRL
MA8
INTV2(1.5V)
THYRQ
TMFLG
MSI2ROTA
YO3
MCDA4
CCDMODE0
MSSCK
INTV6(1.5V)
N.C.
YO1
IOGND1(3V)
IOVDD6(3.0V)
AMC
MSCSR
LDIR
TEST3
TEST2
VITOUT
IOVDD1(3.0V)
MSO2MC
PLLMSK
INTG6(1.5V)
ADA
T
AOUT0
A
TFSMPL
MCDA5
N.C.
N.C.
TEST
N.C.
CO1
MCHA0
MCDA2
INTV1(1.5V)
RECA1
VRT
WRX
SPCKO
XACC
INTV8(1.5V)
PLLSGND
IOVDD2(3.0V)
RECA2
INTG9(1.5V)
DICO_DVDD
LBUS2
TGCK
IOGND4(3.0V)
ADDT3
IOVDD5(3.0V)
LBUS0
PLLRGND
IOGND5(3.0V)
PLLRVDD
NC
INTG4(1.5V)
BUNRI
OGND
PCOR
RECDT
ADDT2
MDQ6
INTV5(1.5V)
FRA
T_REFO
OSCVDD
OSCOUT
DRP
ADDT5
INTG5(1.5V)
DICK
ADA
T
AIN0
MDQ2
INTG2(1.5V)
RFIN
VRB
MDQ7
IOGND6(3.0V)
MDQ0
TRST
DICO_AVDD
ADVDD
YI3
N.C.
MDQ3
MCDA0
LRCK
DGND
IOVDD3(3.0V)
MCHA1
YI1
FS_EDGE_REF
CI2
CO0
ADATAIN1
CI0
PLLSVDD
N.C.
HCO
N.C.
CI3
SCWIN
N.C.
ADATAOUT1
INTG1(1.5V)
INTG8(1.5V)
IOVDD4(3.0V)
RECCKO
CI1
MCDA6
CO3
TRRT
XRST
INTV4(1.5V)
OVDD
YI2
MCDA3
PBCK
CO2
FLAT_SYNC
TRRV
PLLSW
YI0
MCCE
OSCIN
RDX
SMC
IOGND2(3.0V)
ADDT0
N.C.
N.C.
N.C.
N.C.
ADDT1
MDQ8
MDQ4
ADDT4
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(12/21)
(16/21)
(13/21)
(4/21)
(21/21)
(13/21)
(10/21)
(13/21)
(9/21)
(4/21)
(13/21)
(13/21)
(9/21)
(10/21)
IC6401
DV SIGNAL PROCESS
CSP(CHIP SIZE PACKAGE)IC
(19/21)
(3/21)
(4/21)
(12/21)
(13/21)
(15/21)
(13/21)
(14/21)
(21/21)
(4/21)
SIGNAL
REC
PB
CHROMA
SIGNAL PATH
VIDEO SIGNAL
AUDIO
Y
Y/CHROMA
Ref.signal
PB
REC/PB
SIGNAL PATH
REC
DV SIGNAL PROCESS(R BLOCK)
VC-352 BOARD(8/21)
XX MARK:NO MOUNT
I
3
H
15
10
J
7
F
13
C
5
G
D
B
E
9
14
11
12
16
K
6
8
4
17
18
2
16
@20
@62
@63
@31
@56
@57
@29
@32
@58
@59
@60
@61
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