Read Sony DCR-HC65 Service Manual online
DCR-HC65
4-2. SCHEMATIC DIAGRAMS
VC-359 BOARD SIDE A
VC-359 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-359 BOARD SIDE A
VC-359 BOARD SIDE B
4-27
4-28
VC-359 (1/21)
SECTION 4
PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS
4-2. SCHEMATIC DIAGRAMS
For Schematic Diagram
• Refer to page 4-93 for printed wiring board.
• Refer to page 4-93 for printed wiring board.
R1.4/P2.8
R1.4/P2.8
2.7
2.7
0
2.8
2.8
R1.2/P0
R2.2/P0
4.7
3.4
2.9
3.4
2.8
3.5
4.7
4.7
1.3
R0/P2.8
R0/P2.8
R1.1/P2.8
R1.2/P2.8
R1.3/P2.8
R1.5/P2.8
R1.6/P2.8
R1.6/P2.8
R1.5/P2.8
R1.3/P2.8
R1.4/P2.8
R1.4/P2.8
R0.7/P1.8
R0.6/P1.8
0
2.8
2.8
2.8
2.8
R1.4/P0
2.8
2.8
2.8
2.8
NO MARK:REC/PB MODE
R :REC MODE
P :PB MODE
R :REC MODE
P :PB MODE
:Voltage measurement of the CSP IC
and the Transistors with mark,is
not possible.
not possible.
10uH
L5002
0uH
FB5003
R5024
56
CAM_SI
CAM_15V
C5015
XX
0.1u
B
C5004
R5017
68
0
R5037
3.3u
25V
C5002
CAM_3.1V
0uH
FB5001
AD9
10uH
L5003
AD3
4.7u
B
C5009
0
R5022
XX
R5048
TG_HD
22u
4V
4V
C5016
P
0
R5047
XX
C5007
A_4.6V
AD80053KSTRL-36
IC5003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36
37
38
39
40
41
42
43
44
45
46
47
48
R5015
0
0.1u
B
C5020
A_2.8V
0
R5050
TG_FLD
0
R5043
470
R5046
1u
B
C5022
B
1u
C5017
0.01u
B
C5021
AD6
IC7101_Y_OUT
XX
R5011
10
R5026
R5003
100k
B
0.1u
C5006
CH_SO
B
0.1u
C5005
XX
R5008
AD2
0.1u
B
C5029
0
R5049
HN1B04FE-Y/GR(TPLR3)
Q5003
3
5
4
6
2
1
ADCK27
4.7u
B
C5030
10k
R5045
TG_VD
CAM_-7.5V
R5013
0
0
R5038
R5019
10
CLPOB
10u
6.3V
6.3V
C5019
P
R5033
XX
L5001
10uH
AD4
0.1u
B
C5026
4V
22u
C5027
TA
P
0.1u
B
C5013
0.1u
B
C5025
0uH
FB5005
AD11
D_2.8V
TK11134CSCL-G
IC5002
1
2
3
45
0
R5029
0uH
FB5002
AD10
0
R5020
CLPVO
220
R5018
AD7
0
R5010
100
R5023
0.001u
B
C5010
CAM_SO
CAM_CS
AD12
10u
6.3V
C5028
P
XSYS_RST
TG_ID
VSG1
100k
R5005
R5004
0
10u
10V
C5003
A
CHCK
AD0
AD8
CH_CS
B
1u
C5011
REG_GND
CH_SCK
ZV1
CAM_SCK
0.1u
B
C5012
AD1
R5014
100k
CK_CONT
22u
4V
C5018
P
0uH
FB5006
AD5
0.1u
B
C5024
0uH
FB5004
AD13
10k
R5042
XX
C5031
R5012
0
CXD3623GA-T4
IC5001
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
B
0.1u
C5008
680
R5044
X5001
66MHz
1
4
3
2
2
1u
B
C5023
1u
B
C5032
10uH
L5004
0
R5009
CAM_DD_ON
10
R5006
0
R5016
0
R5025
10
R5027
0
R5030
R5031
0
33P
CN5001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
0uH
FB5007
0uH
FB5008
0uH
FB5009
100p
CH
C5033
100p
CH
C5034
PITCH_AD
YAW_AD
VST_C_RESET
CSUB
CLPDM
1
A
CAM_SO
H2
RG1_OUT
TG_ID
CAM_CS
CAM_SO
TG_VD
VSG1
ZV1
H1
TG_VD
CAM_SCK
CAM_SCK
TG_FLD
TG_FLD
TG_HD
LH11
CAM_CS
VSG1
ZV1
TG_HD
CAM_SI
CK_CONT
TG_ID
CAM_SI
AD13
AD11
AD10
AD10
AD9
AD11
AD8
AD0
AD2
AD1
AD6
AD7
AD0
AD8
AD9
CH_SO
AD12
CH_SCK
AD12
AD7
AD1
AD2
AD5
CH_CS
AD3
AD4
AD4
AD3
AD5
AD13
AD6
CHCK
SHP1
SHD1
LH11
RG1_OUT
H1
CLPDM
CK_CONT
CLPOB
H2
SHD1
SHP1
CSUB
YAW_AD
VST_C_RESET
PITCH_AD
CH_CS
CH_SCK
CH_SO
CHCK
CLPOB
VST_C_RESET
YAW_AD
PITCH_AD
CLPDM
CSUB
VSS4
VHOLD
VH
TEST2
VSS9
TRST
H2
VSS6
AVD3
VSS5
VSS7
CHCK
V4
DLLSEL
SSI
XSHP2
TGFLD
SCK
CLPDM
XSHD1
HPHASE
RG2
LH12
NC
TEST1
TGVD
ZSG1
H3
VSTRAGE
TEST4
OSCO
A
VD8
VSS0
ID
DLLRST
SHT
H4
AVD5
AVD4
CK
SSO
XSHD2
RST
AVD7
CKCNT
ZV1
TEST0
A
VD2
NC
VSS1
DSGA
T
A
VD0
AVD6
VDD0
SEN
VARHDR1
V1
A
VS0
VL
V3
V2
XSHP1
OSCI
TGHD
VSS2
V
ARHDR0
VSS3
VSS8
VM
VSS10
VDD2
A
VD9
CCDSL
LH11
TEST3
VDD1
ZCHCK
RG1
A
VD1
H1
DVDD
CLPREF
CLPBYP
D12
CLPDM
PBLK
SHD
D3
AGC IN+
CHROMA-IN
SEN
D9
D7
D0
ADCCLK
D5
DVSS
D2
SDL
ACVDD
D6
D1
D11
ACVSS
ADVDD
RST
D10
VD
SLM
ACVSS
LINE-IN
SDATA
SVSS
VRT
CLPOUT
ADVSS
DRVSS
AGC IN-
DRVDD
VRB
CLPOB
HD
SCLK
D8
SHP
SVDD
D4
D13
A_2.8V
GND
CCD_OUT-
YAW_AD
CCD_OUT+
GND
XSHD
REG_GND
LH
V3
CLPDM
GND
H1
A_2.8V
REG_GND
VST_C_RESET
GND
GND
REG_GND
XSHP
GND
V2
CAM_15V
H2
GND
GND
RG
PITCH_AD
CAM_-7.5V
RCSUB
V1
VSUB
V4
IC5001
TIMING GENERATOR
CSP(CHIP SIZE PACKAGE)IC
S/H,AGC,A/D
IC5003
TO
CD-513 BOARD
CN201
CD-513 BOARD
CN201
THROUGH THE
FP-913
FLEXIBLE
FP-913
FLEXIBLE
(19/21)
@01
@03
(3/21)
(4/21)
(14/21)
(7/21)
@02
(6/21)
(19/21)
3.4V REG
IC5002
@04
(13/21)
(3/21)
@05
(2/21)
(3/21)
(3/21)
(2/21)
@06
@07
(4/21)
(13/21)
@08
(13/21)
(13/21)
(4/21)
(13/21)
(4/21)
(3/21)
@09
@10
(3/21)
(4/21)
@11
(11/21)
@12
XX MARK:NO MOUNT
TIMING GENERATOR,S/H,AGC,A/D CONV.(CH BLOCK)
VC-359 BOARD(1/21)
16
Y/CHROMA
REC
SIGNAL PATH
PB
CHROMA
Y
VIDEO SIGNAL
I
3
H
15
10
19
J
7
F
13
C
5
G
D
B
E
9
14
11
12
16
K
6
8
4
17
18
2
BUFFER
(PAGE 4-7
of LEVEL2)
of LEVEL2)
ea
IC5003
qh
(CAMERA)
30.3 ns
3.8 Vp-p
e;
FB5004
15.1 ns
3.6 Vp-p
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