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DVP-S9000ES
3-7
3-8
3-4. SIGNAL PROCESS 2 BLOCK DIAGRAM
IC702
MIP
IC802
OSD
23
20
75
76
21
19
77
100
84
63
ı
70
PDO0 – 7
PDO0 – 7
CS4X
FBIWAIT
FBIINT
FIDOUT
27MFBI
HSYNCO
VS30
FLDO
HSYNC
X3VRST
27M32
CS2X
CS3X
WRH
RD
XRST
HD0 – 15
HA0 – 21
XCSI
YC1I0 – 7
XWAITO
XHD1I
XVD1I
XINTO
FD1I
CLKX
CLK1
22 36
221
60
XWRI
XRDI
XRST
DATAIO 0
–
15
ADRSI 0
–
7
24 – 27
30 – 33
38 – 43
48 49
54 – 61
SIGNAL
PROCESS 1
(SEE PAGE 3-6)
SYSTEM
CONTROL
(SEE PAGE 3-13, 14)
SIGNAL
PROCESS
(SEE PAGE 3-6)
SYSTEM
CONTROL
(SEE PAGE 3-13, 14)
SIGNAL
PROCESS 1
(SEE PAGE 3-6)
IC804, 805
192 193
195 – 198
200 – 203
205 – 208
210 – 213
215 – 218
157 – 160
162 – 165
167 168
170 171
173 174
176 177
143 144
146 147
149 151
152 154
155
124 125
127 128
130 131
133 134
136 137
139 140
232 – 235
237 – 240
2 – 5
7 – 10
116
ı
123
92
ı
95
97
97
ı
100
50
ı
53
55
55
ı
58
220
231
87
88
122
180
182
190
191
HRWB
PDI0 – 7
DVO0 – 7
PD400 – 407
27M
YC300 – 307
HCSB
RSTB
FLDO
HSYNCO
TRST
CLKI
SCLKIN
HAD23
HAD22
FLDO
HSYNC
X3VRST
27M32
CS2X
CS3X
16M SDRAM
05
D1CLKO
223
OSDINT
27M
HIREQO
224
OSDWT
HWAITOB
228
DACK1
DM ACKO
229
DREQ1
DM REQO
VIDEO 1
(SEE PAGE 3-9)
SYSTEM
CONTROL
(SEE PAGE 3-13, 14)
HD0
–
15
HA1
–
8
HD0
–
15
HA0
–
21
PD300 – 307
MB-91 BOARD (3/8)
(SEE PAGE 4-35 to 4-40)
SDAD0
–
11
SDDT0
–
11
DQML, DQMU,
CLK, CKE,
WE, CAS,
RAS, CS
3.4 Vp-p (27 MHz)
IC802
<z,/
,<z,x
3.5 Vp-p (27 MHz)
IC802
y;
3.2 Vp-p (H)
IC802
ik
3.6 Vp-p (27 MHz)
IC702
if
,<z//
3.2 Vp-p (V)
IC702
uh
3.2 Vp-p (H)
IC702
ug
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