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2-1-1. Attenuation of OP Output Signals
The RF signals (RFP, RFM) output from OP for DVD are attenuated by R066 and
R064 so that they satisfy the input amplitude allowable level of IC006 in the post
stage.
(About 1V
R064 so that they satisfy the input amplitude allowable level of IC006 in the post
stage.
(About 1V
PPD
(*3) for SL (*1) disc. In actual, only the RFP signal is output be-
cause RFM signal is connected to the ground in the OP block.
2-1-2. HPF
Low frequency component of the attenuated RF signal is removed by a high pass
filter (HPF) that cuts off the frequency (about 3.16kHz) determined by the input
impedance of C046, C047, and IC006, then it is entered to the IC001.
filter (HPF) that cuts off the frequency (about 3.16kHz) determined by the input
impedance of C046, C047, and IC006, then it is entered to the IC001.
2-1-3. RF Front End Processing: IC001 SSI33P3720
(1) ATT block
The RF signal entered from IC006 RFP^£ and RFN^¢ is entered to the ATT
block. In this block, this processing is executed to attenuate the signal below
signal amplitude level determined according to the specification (about
200mV
block. In this block, this processing is executed to attenuate the signal below
signal amplitude level determined according to the specification (about
200mV
PPD
, determined depending on AGC input allowable level) in order to
utilize high performance of IC.
After processing, the signal is output from IC006 ATOP^™ and ATON^¡.
After processing, the signal is output from IC006 ATOP^™ and ATON^¡.
ATT: Set to 3/16 for SL disc, or 5/16 for DL (*2) disc.
These are operated by the command register set via serial interface.
(2) AGC block
ATT output IC006 ATOP^™ and ATON^¡ are processed below AGC allow-
able level as mentioned above, then they are AC-coupled by C050 and C051,
and entered respectively to AGC block input IC001 AIP%ª and AIN^º.
The AGC block controls gain of AGC amplifier so that constant input signal
(1V
able level as mentioned above, then they are AC-coupled by C050 and C051,
and entered respectively to AGC block input IC001 AIP%ª and AIN^º.
The AGC block controls gain of AGC amplifier so that constant input signal
(1V
PPD
) is supplied to the IC006 DIP%£ and DIN%¢. The AGC compares
full-wave rectified input signal to IC006 DIP%£ and DIN%¢ with reference
level, and repeats decay and attack while keeping a balance with the product
of current by time so as to attain the optimum gain.
level, and repeats decay and attack while keeping a balance with the product
of current by time so as to attain the optimum gain.
Decay: When input signal to IC006 DIP%£ and DIN%¢ is below 1V
PPD
,
C052 (C
BYP
) is discharged with 4
µ
A decay current. In this case,
AGC amplifier gain gradually increases.
Attack: When input signal to IC006 DIP%£ and DIN%¢ is over 1V
PPD
, C052
(C
BYP
) is charged with 0.18mA attack current. In this case, AGC
amplifier gain gradually decreases.
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