Read Sony BDP-CX7000ES Service Manual online
BDP-CX7000ES
115
Pin No.
Pin Name
I/O
Description
G13
GND
-
Ground terminal
G14
VOCK
O
Video clock signal output to the HDMI transmitter
H1
GND
-
Ground terminal
H2
STEST10
I
Not used
H3
LED_TEST3
O
Not used
H4
VDD15
-
Power supply terminal (+1.5V)
H11
VDD15
-
Power supply terminal (+1.5V)
H12
GND
-
Ground terminal
H13, H14
VOD7, VOD8
O
Digital video signal output to the HDMI transmitter
J1
TEN
I
Enable signal input terminal (for JTAG) Not used
J2
STEST5
I
Not used
J3
LED_TEST4
O
Not used
J4
STEST4
I
Not used
J11
VDD15
-
Power supply terminal (+1.5V)
J12
GND
-
Ground terminal
J13, J14
VOD5, VOD6
O
Digital video signal output to the HDMI transmitter
K1, K2
VIDC9, VIDC8
I
Digital video (Cb/Cr) signal input from the FPGA
K3
LED_TEST5
O
Not used
K4
STEST3
I
Not used
K11
GND
-
Ground terminal
K12
VDD15
-
Power supply terminal (+1.5V)
K13, K14
VOD3, VOD4
O
Digital video signal output to the HDMI transmitter
L1, L2
VIDC7, VIDC6
I
Digital video (Cb/Cr) signal input from the FPGA
L3
LED_TEST6
O
Not used
L4
VDD15
-
Power supply terminal (+1.5V)
L5
GND
-
Ground terminal
L6, L7
VDD15
-
Power supply terminal (+1.5V)
L8
GND
-
Ground terminal
L9
VDD15
-
Power supply terminal (+1.5V)
L10
STEST2
I
Not used
L11
GND
-
Ground terminal
L12
VDD15
-
Power supply terminal (+1.5V)
L13, L14
VOD1, VOD2
O
Digital video signal output to the HDMI transmitter
M1, M2
VIDC5, VIDC4
I
Digital video (Cb/Cr) signal input from the FPGA
M3
GND
-
Ground terminal
M4
LED_TEST7
O
Not used
M5, M6
TMC1, TMC2
I
Mode control signal input terminal (for JTAG) Not used
M7
VDD33
-
Power supply terminal (+3.3V)
M8
GND
-
Ground terminal
M9, M10
N.C
-
Not used
M11
GND
-
Ground terminal
M12
VDD33
-
Power supply terminal (+3.3V)
M13
VOVS
O
Vertical sync signal output to the HDMI transmitter
M14
VOD0
O
Digital video signal output to the HDMI transmitter
N1
VIDC3
I
Digital video (Cb/Cr) signal input from the FPGA
N2
GND
-
Ground terminal
N3
VIDC1
I
Digital video (Cb/Cr) signal input from the FPGA
N4 to N8
VIDY9, VIDY7, VIDY5,
VIDY3, VIDY1
I
Digital video (Y) signal input from the FPGA
N9
VIVS
I
Vertical sync signal input from the FPGA
N10
VICK
I
Video clock signal input from the FPGA
N11
STEST1
I
Not used
N12
TRST
I
Reset signal input terminal (for JTAG) Not used
N13
GND
-
Ground terminal
N14
VOHS
O
Horizontal sync signal output to the HDMI transmitter
P1
VDD33
-
Power supply terminal (+3.3V)
P2, P3
VIDC2, VIDC0
I
Digital video (Cb/Cr) signal input from the FPGA
P4 to P8
VIDY8, VIDY6, VIDY4,
VIDY2, VIDY0
I
Digital video (Y) signal input from the FPGA
P9
VIHS
I
Horizontal sync signal input from the FPGA
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