Read Sony MEX-N4000BE / MEX-N4000BT / MEX-N4050BT / MEX-N4070BT Service Manual online
MEX-N4000BE/N4000BT/N4050BT/N4070BT
50
Pin No.
Pin Name
I/O
Description
62
DVSS5
-
Ground terminal
63
VDD1-3
-
Power supply terminal (+1.5V)
64
VSS-2
-
Ground terminal
65
XVSS3
-
Ground terminal
66
XI
I
System clock input terminal (16.9344 MHz)
67
XO
O
System clock output terminal (16.9344 MHz)
68
XVDD3
-
Power supply terminal (+3.3V)
69
ADVDD3
-
Power supply terminal (+3.3V)
70
ADIN1 (IN_L-CH)
I
Audio signal (L-ch) input from the electrical volume
71
ADVREFL
O
Reference voltage output terminal
72
ADVCM
O
Reference voltage output terminal
73
ADVREFH
O
Reference voltage output terminal
74
ADIN2 (IN_R-CH)
I
Audio signal (R-ch) input from the electrical volume
75
ADVSS3
-
Ground terminal
76
MS
I
Microprocessor interface mode selection signal input terminal
“L”: serial interface, “H”: parallel interface Fixed at “L” in this unit
“L”: serial interface, “H”: parallel interface Fixed at “L” in this unit
77, 78
CD_BUS0, CD_BUS1
I/O
Serial data input/output terminal Not used
79
CD_BUS2
O
Serial data output to the system controller
80
CD_BUS3
I
Serial data input from the system controller
81
CD_BUCK
I
Serial data transfer clock signal input from the system controller
82
CD_XCCE
I
Chip enable signal input from the system controller
83
VDD3-2
-
Power supply terminal (+3.3V)
84
VSS-3
-
Ground terminal
85
/RST
I
Reset signal input from the system controller “L”: reset
86
VDD1-4
-
Power supply terminal (+1.5V)
87
DEC_INT
O
Interrupt signal output to the system controller
88
BSIF_INT
O
Request signal output to the system controller
89
BSIF_GATE
I
Gate signal input from the system controller
90
BSIF_DATA
I
Audio data input from the system controller
91
BCK_IN_F
I
Bit clock signal input from the system controller
92
LRCK_IN_F
I
L/R sampling clock signal input from the system controller
93
DEC_XMUTE
I
Muting on/off control signal input from the system controller “L”: muting on
94
ZDET
O
Zero data detection signal output to the system controller
95
SP_DATA
O
Serial data output to the system controller
96
SP_CLK
I
Serial data transfer clock signal input from the system controller
97
TEST
I
Test mode setting terminal Normally fi xed at “L”
98
PDO
O
EFM and PLCK phase difference signal output terminal
99
TMAX
O
TMAX detection result output terminal
100
LPFN
I
PLL circuit low-pass fi lter amplifi er inversion input terminal
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