Read Sony MDX-C7890R Service Manual online
– 43 –
5-7.
IC PIN FUNCTION DESCRIPTION
•
SERVO BOARD IC301 CXD2652AR
Pin No.
Pin Name
I/O
Function
1
MNT0
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2
O
Monitor 2 signal output to the MD mechanism controller (IC501)
4
MNT3
O
Monitor 3 signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“H”: recording mode, “L”: playback mode (fixed at “L” in this set)
“H”: recording mode, “L”: playback mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
15
TX
I
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode (for optical in) Not used (fixed at “L”)
22
DOUT
O
Digital audio signal output terminal when playback mode (for optical out) Not used (open)
23
ADDT
I
Recording data input terminal Not used (fixed at “L”)
24
DADT
O
Playback data output terminal Not used (open)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
26
XBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
27
FS256
O
Clock signal (11.2896 MHz) output to the PCM1717E (IC202)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29
A03
O
30
A02
O
31
A01
O
32
A00
O
33
A10
O
Address signal output to the external D-RAM Not used (open)
34
A04
O
35
A05
O
36
A06
O
Address signal output to the D-RAM (IC307)
37
A07
O
38
A08
O
39
A11
O
Address signal output to the external D-RAM Not used (open)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Address signal output to the D-RAM (IC307)
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