MDX-C670, MDX-C670RDS (serv.man2) - Sony Car Audio Service Manual (repair manual). Page 9

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3.
IC  PIN  FUNCTION  DESCRIPTION
3-1.   SERVO  BOARD  IC501  CXP84340-049Q  (MD MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1
TIN3
I/O
2
TIN4
I/O
Input of 4
×
8 matrix test keys
3
TIN5
I/O
(“L” is always output, except in TEST mode)
4
TIN6
I/O
(Not used in this set) (open)
5
TIN7
I/O
6
LOAD
O
Output of control for loading motor (M903) (Cartridge loading direction)
7
EJECT
O
Output of control for loading motor (M903) (Cartridge eject direction)
8
NCO
O
Not used (open)
9
NCO
O
10
MDMON
O
Mechanical deck power ON
11
E SW
I
Input of loading end switch (S902)
“L”: Switch make
12
AGING
O
Output of aging status in TEST mode
“H”: Aging completed
“L”: Under aging
(Not used in this set)
13
AGCHK
O
Output of status when aging completed in TEST mode
“H”: Aging OK
“L”: Aging NG (Not used in this set)
14
TFTON
O
Output of free run status in TEST mode
“H”: Free run
“L” : Normal  (Not used in this set)
15
NCO
O
16
NCO
O
Not used (open)
17
NCO
O
18
DFCTSEL
I
Select whether DEFECT2 function is used for CXD2650R (IC301)
“H”: Not used
“L”: Used
19
DPLLSEL
I
Select whether DPLL function is used for CXD2650R (IC301)
“H”: Not used
“L”: Used
20
EMPHSEL
I
Select whether Emphasis signal is output from pin or UNILINK
“H”: Output from pin
“L”: Output from both pin and UNILINK
21
LOCK
O
Output of CLV LOCK status in TEST mode
“H”: LOCK
“L”: UNLOCK
22
NCO
O
Not used (open)
23
2M/4M
I
Select DRAM 2M or 4M
“H”: 2M (internal DRAM)
“L”: 4M (external DRAM)
24
TAEG E
O
Output of mechanism aging completion in TEST mode (Not used in this set) (open)
25
NCO
O
Not used (open)
26
MNT0
I
Input of CXD2650R (IC301) monitor 0
27
MNT1
I
Input of CXD2650R (IC301) monitor 1
28
MNT2
I
Input of CXD2650R (IC301) monitor 2
29
MNT3
I
Input of CXD2650R (IC301) monitor 3
30
RESET
I
Input of RESET signal
31
EXTAL
I
Input of SYSTEM CLOCK (10 MHz)
32
XTAL
O
Output of SYSTEM CLOCK (10 MHz)
33
VSS
Ground
34
TX
O
Output of CLOCK signal (32 kHz) for clock (Not used in this set) (open)
35
TEX
I
Input of CLOCK signal (32 kHz) for clock (Not used in this set) (Connected to the GND)
36
AVSS
Ground pin for A/D conversion input
37
AVREF
Input pin for A/D conversion input reference voltage
38
INIT
I
Initial input at the reset
– 11 –
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