Read Sony SCD-XE680 Service Manual online
54
SCD-XE680
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used
61
PHREFI
I
Clock signal (2.8224 MHz) input from the programmable logic device
62
PHREFO
O
Phase reference signal output terminal for DSD output phase modulation Not used
63
ZDFL
O
Front L-ch Zero data flag detection signal output to the programmable logic device
64
DSAL
O
Front L-ch DSD data output to the digital filter
65
ZDFR
O
Front R-ch Zero data flag detection signal output to the programmable logic device
66
DSAR
O
Front R-ch DSD data output to the digital filter
67
VDDSD
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital filter
70
ZDFLFE
O
Sub woofer zero data flag detection signal output terminal Not used
71
DSASW
O
Sub woofer DSD data output to the digital filter
72
VSDSD
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Surround L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Surround L-ch DSD data output to the digital filter
75
ZDFRS
O
Surround R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Surround R-ch DSD data output to the digital filter
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSC
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDC
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIO
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip interface
Not used
Not used
90
VDIO
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface Not used
93
IBCK
O
Data transmission clock signal output terminal for IEEE 1394 link chip interface Not used
94
VSC
—
Ground terminal (for core)
95
TESTI
I
Input terminal for the test (normally: fixed at “H”)
96
TESTI
I
Input terminal for the test (normally: fixed at “L”)
97
TESTI
I
Input terminal for the test (normally: fixed at “H”)
98
TESTO
O
Output terminal for the test (normally: open)
99
VDC
—
Power supply terminal (+2.5V) (for core)
100 to 105
TESTI
I
Input terminal for the test (normally: fixed at “L”)
106
VSIO
—
Ground terminal (for I/O)
107 to 109
TESTI
I
Input terminal for the test (normally: fixed at “L”)
110
VDIO
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for disc inspection mode from the programmable logic device
116
VSC
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDC
—
Power supply terminal (+2.5V) (for core)
122
TESTI
I
Input terminal for the test (normally: fixed at “L”)
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