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61
SCD-XE670
•
MAIN BOARD IC801 CXD2752R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSC
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the CPU (IC901)
3
MSCK
I
Serial data transfer clock signal input from the CPU (IC901)
4
MSDATI
I
Serial data input from the CPU (IC901)
5
VDC
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the CPU (IC901)
7
MSREADY
O
Ready signal output to the CPU (IC901) “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used (open)
9
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
10
SMUTE
I
Muting on/off signal input from the CPU (IC901) “H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input terminal
12
VSIO
—
Ground terminal (for I/O)
13
EXCKO1
O
External clock 1 signal output terminal Not used (open)
14
EXCKO2
O
External clock 2 signal output terminal Not used (open)
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal Not used (open)
16
FRAME
O
Frame signal output terminal Not used (open)
17
VDIO
—
Power supply terminal (+3.3V) (for I/O)
18 to 21
MNT0 to MNT3
O
Monitor signal output terminal Not used (open)
22 to 25
TESTO
O
Output terminal for the test (normally: open)
26
TCK
I
Clock signal input terminal for the test (normally: fixed at “L”)
27
TDI
I
Input terminal for the test (normally: open)
28
VSC
—
Ground terminal (for core)
29
TDO
O
Output terminal for the test (normally: open)
30
TMS
I
Input terminal for the test (normally: open)
31
TRST
I
Reset terminal for the test (normally: fixed at “L”)
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDC
—
Power supply terminal (+2.5V) (for core)
36
TESTO
O
Output terminal for the test (normally: open)
37
XBIT
O
Monitor terminal relative to DST Not used (open)
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used (open)
42
VSIO
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used (open)
45
VDIO
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used (open)
48
XSUPAK
O
Supplementary data acknowledge signal output terminal Not used (open)
49
VSC
—
Ground terminal (for core)
50
TESTO
O
Output terminal for the test (normally: open)
51, 52
TESTI
I
Input terminal for the test (normally: fixed at “L”)
53
TESTO
O
Output terminal for the test (normally: open)
54
VDC
—
Power supply terminal (+2.5V) (for core)
55, 56
TESTO
O
Output terminal for the test (normally: open)
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
58
VSDSD
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input for DSD data output from the CXD9647R (IC803)
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