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77
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
RFAC
I
EFM RF signal (AC level) input from the CXD1881R (IC001)
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input of the EFM playback master PLL
53
FILO
O
Filter output for master clock of the playback EFM master PLL
54
FILI
I
Filter input for master clock of the playback EFM master PLL
55
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
58
VCTL
I
Control voltage input terminal for the variable pitch Not used (fixed at “L”)
59
V16M
O
16.9344 MHz clock signal output Not used (open)
60
VPCO
O
PLL charge pump output terminal for the variable pitch Not used (fixed at “L”)
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Playback EFM asymmetry circuit on/off selection signal input terminal
Not used (fixed at “H”)
Not used (fixed at “H”)
63
MD2
I
Digital out on/off control signal input from the CPU (IC901)
“L”: digital out on, “H”: digital out off
“L”: digital out on, “H”: digital out off
64
DOUT
O
Digital audio signal output to the DIGITAL (CD) OUT OPTICAL (IC442)
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital filter (IC101, 201, 1101, 1201, 2101,
2201), SACD decoder (IC701), and CXD9647R (IC803)
2201), SACD decoder (IC701), and CXD9647R (IC803)
66
PCMD
O
Serial data output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201), SACD decoder
(IC701), and CXD9647R (IC803)
(IC701), and CXD9647R (IC803)
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201),
SACD decoder (IC701), and CXD9647R (IC803)
SACD decoder (IC701), and CXD9647R (IC803)
68
EMPH
O
Playback disc output terminal in emphasis mode Not used (open)
69
XTSL
I
Input terminal for the system clock frequency setting Fixed at “H” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.86688 MHz)
72
XTAO
O
System clock output terminal (33.86688 MHz) Not used (open)
73
SOUT
O
Not used (open)
74
SOCK
O
Not used (open)
75
XOLT
I
Not used (open)
76
SQSO
O
Subcode Q data output to the CPU (IC901)
77
SQCK
I
Subcode Q data reading clock signal input from the CPU (IC901)
78
SCOR
O
Not used (open)
79
SBSO
O
Subcode serial data output to the SACD decoder (IC701)
80
EXCK
I
Subcode serial data reading clock signal input to the SACD decoder (IC701)
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