Read Sony PCM-M1 Service Manual online
— 45 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
O
O
—
O
O
O
O
O
O
I
O
I
—
I
O
O
I
O
O
O
I
I
O
O
O
O
O
O
O
I
O
I
O
I
I
I
I
—
O
O
O
I
O
I
I
I
O
O
I
I
Description
+5v
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM write enable signal output.
External RAM output enable signal output.
External addressing enable signal output.
Test input, fixed to “L”.
X’tal oscillator circuit -1 output (not used).
X’tal oscillator circuit -1 input (not used).
GND.
Reset input. Reset at “L”.
System clock output (Frequency is 4.9152 MHz when SELC = “L”, 8.192 MHz when SELC = “H”).
* 1 control byte (1). Q code decode (music interval detection) output when bit 1 = “L”, BCK clock output from
RX-PLL when bit 1 = “H”).
ATF sync signal input.
Channel clock (fch) output.
Signal output with duty 50 at SBSY rate.
Control byte (1). Data transfer monitoring signal output with microprocessor when bit 1 = “L” (Transfer is
enabled at “L”), f256 clock output from RX-PLL when bit 1 = “H”).
Clock input for data transfer with microprocessor.
Serial data input from microprocessor.
Serial data output to microprocessor.
Frame cycle signal output for data transfer with microprocessor.
PLL clock divided-by-5880 output.
9.8304 MHz output when SELC = “L”, 12.288 MHz output when SELC = “H”.
Mute input, mute at “H”. REC monitor sound is not muted.
Mute monitor. The mute status is indicated by “H”.
RXPLL lock monitor signal output. Indicates the RXPLL is locked.
Playback RF signal control (RF signal is valid at “L”, RF signal is invalid at “H”.)
Monitor signal indicating result of CI check which supports RF.
Oscillating frequency selection signal input.
Control byte (1). RFPLL clock output when bit 1 = “L”, f128 clock output from RX-PLL when bit 1 = “H”).
Test terminal, fixed to “L”.
Playback RF signal input.
Chip select input for data transfer with microprocessor. Transfer enable at “L”.
RF switching pulse. “A” track at “L”. “B” track at “H”.
GND.
ATF pilot signal of wiring signal/identification signal output. Pilot signal at “H”.
REC/PB discriminating signal input. REC state at “H”.
Wiring signal output.
Test terminal, fixed to “L”.
Phase comparator output for RXPLL.
Oscillating frequency selection signal input.
Mute input, mute at “H”. REC monitor sound is also muted.
External VCO clock input of RXPLL. (512 fs reference).
Phase comparator signal output for RXPLL. (2 fs generated from PLL clock).
Phase comparator signal output for RXPLL. (2 fs of rxx sync detection signal).
Master mode/slave mode select. Master at “H”.
Digital interface signal input.
Pin Name
Vpp
A10
A11
A12
A13
A14
XWE
WOE
XEAN
TST1
XT10
XT11
Vss
XRST
CLKO
MINT
ATSY
MCLK
DREF
SBPM
EXCK
SDSI
SDSO
SBSY
RFPL
CCLK
MUTE
MUTM
UNLK
RFCT
SYMN
SELB
PLCK
TST2
RFDT
XCS
SWP
Vss
PIPC
REPB
REDT
TST4
PDO
SELC
MUTA
PLCO
PLVR
PLRF
MSSL
RX
4-7.
IC PIN FUNCTION
• IC506 CXD2607BR
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