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NW-S202/S202F/S203F/S205F
12
12
NW-S202/S202F/S203F/S205F
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
For Printed Wiring Boards.
Note:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• f : internal component.
•
• Y : parts extracted from the conductor side.
• f : internal component.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
• MAIN board is multi-layer printed board.
However, the patterns of intermediate-layer have not been
However, the patterns of intermediate-layer have not been
included in diagram.
• Lead Layouts
For Schematic Diagrams.
Note:
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics and
50 WV or less are not indicated except for electrolytics and
tantalums.
• All resistors are in Ω and 1/4 Ω or less unless otherwise
specified.
• f : internal component.
• C : panel designation.
• C : panel designation.
• A : B+ Line.
• Power voltage is dc 3.7 V and fed with regulated dc power
• Power voltage is dc 3.7 V and fed with regulated dc power
supply from CN601 pin 1 and pin 2 on the MAIN board.
• Voltages are dc with respect to ground under no-signal
conditions.
no mark: PLAYBACK
• Voltages are taken with a VOM (Input impedance 10 MΩ).
• Voltage variations may be noted due to normal production
• Voltages are taken with a VOM (Input impedance 10 MΩ).
• Voltage variations may be noted due to normal production
tolerances.
• Signal path.
F
F
: AUDIO
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
from that of conventional IC.
* Replacement of IC101 and IC201 on the MAIN board
used in this set requires a special tool.
* Replacement of IC101 and IC201 on the MAIN board
used in this set requires a special tool.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Side B)
(Side B)
the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side A)
(Side A)
the parts face are indicated.
surface
Lead layout of conventional IC
CSP (chip size package)
• IC Block Diagrams
– MAIN Board –
– MAIN Board –
IC201 S71PL032J04BFWOBOB
1
A7
32 DQ6
33 NC
34 A16
35 XCE1F
36 XOE
37 DQ9
38 DQ3
39 DQ4
40 DQ13
41 DQ15
42 NC
31 DQ1
30 VSS
30 VSS
29 A0
SECTOR
SWITCHES
INPUT/OUTPUT
BUFFERS
ERASE VOLTAGE
GENERATOR
2
XLB
3
XWP/ACC
4
XWE
5
A8
6
A11
7
A3
8
A6
9
XUB
10
XRSTF
11
CE2S
12
A19
13
A12
14
A15
48
DQ12
49
DQ7
50
VSS
51
DQ8
52
DQ2
53
DQ1
1
54
NC
55
DQ5
56
DQ14
47
VCCS
46
VCCF
45
DQ10
44
DQ0
43
XCE1S
15
A2
16
A5
17
A18
18
RY
/XBY
19
A20
20
A9
21
A13
22
NC
23
A1
24
A4
25
A17
26
A10
27
A14
28
NC
DATA LATCH
Y-GATING
CELL MATRIX
Y-DECODER
X-DECODER
CHIP ENABLE
OUTPUT ENABLE
LOGIC
VIO
STATE
CONTROL
COMMAND
REGISTER
TIMER
VCC
DETECTER
PGM VOLTAGE
GENERATOR
ADDRESS LA
TCH
1
USB_SUS
22 IU4
23 PG_IO
24 LX_IO
25 IN_IO
26 OUT_CORE
27 IN_CORE
28 LX_CORE
29 PG_AORE
30 EN
21 OUT_IO
USB POWER
MANAGEMENT
2
USB_H/L
3
USB_IN1
4
USB_IN2
5
SYS1
6
SYS2
7
BAT1
8
BAT2
9
XCHG_STAT
10
XCHG_EN
33
IU6
34
IN_USB3.3
35
OUT_USB3.3
36
VL
37
IU7
38
IU8
39
IU9
40
USB_POK
41
SHEELD
32
XCHG_FL
T
31
IU5
11
THM
12
CHG_ISET
13
CT
14
GND
15
IU1
16
IN_AD
17
OUT_AD
18
IU2
19
BP
20
IU3
CORE
STEP-DOWN
REGULATOR
I/O
STEP-DOWN
REGULATOR
REF
1MHz OSC
LI+BATTERY
CHARGER
AND
SYS LOAD SWITCH
USB LDO 3.3V
REGURATOR
REG5
3.3V
A/D LDO 2.0V
REGURATOR
SEQUENCER
(FIGURE 7)
INPUT LIMITER
AND
CHARGER THERMAL
REGULATION
THERMAL-OVERLOAD
PROTECTION ABOVE TJ=+165 C
PWM
IC601 MAX8670A
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