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NW-HD5H
25
25
NW-HD5H
5-7. SCHEMATIC DIAGRAM – MAIN Section (2/7) –
•
See page 32 for IC Block Diagram.
C3011
C3009
C3005
C3006
C3017
C3015
C3018
C3013
C3012
C3010
R3014
R3015
C3001
C3002
R3005
VDR3001
VDR3002
C3003
R3004
C3004
L3001
100
µ
H
100
µ
H
L3002
R3002
R3010
R3006
VDR3003
VDR3004
R3026
R3027
R3028
IC1101
FB1101
C1103
C1101
R1103
R1112
SP3002
SP3003
SP1101
SP1110
TP1110
SP1100
SP1103
SP1104
R3018
IC3001
R3011
C3008
C3007
X3001
R3016
R3017
0.1
0.1
1
0.1
0.1
0.1
0.1
1
0.1
0.1
0
0
0.1
1
0
100p
220
0.1
470k
470k
470k
0
0
0
MBM29SL800BE
-90PT
0.1
100p
100k
0
0
CXR710160-213GH
0
0.1
0.1
22.579MHz
0
1M
GAND_A
GAND_D
GANDHI_CNT
XRESET_1.8V
RDY_XBUSY
XINT_DENDE
DATA_READY
GDAC_PCMD
GDAC_BCK
CDIF_XRDE
3.3V
1.5V
GND
CDIF_LRCK
CDIF_BCK
CDIF_PCMD
DENDE_COMAND
XRESET_DENDE
WAKEUP_DENDE
DENDE_SREQ
GDAC_LRCK
1.9V
DENDE_SS
DENDE_SO
DENDE_SI
DENDE_SCLK
XINT_D
XINT_D
DATA_R
DATA_R
DENDE_S
DENDE_S
WAKEUP_D
WAKEUP_D
XRESET_D
XRESET_D
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GA1
GA9
GA10
GA11
GA12
GA13
GA14
GA15
GA16
GA17
GA20
GA18
GA8
GA7
GA6
GA5
GA4
GA3
GA2
GA19
X
C
S
0
X
R
D
X
W
E
EVA
VDIO0
DVSS0
DVDD0
TEST7
TEST8
DVDD4
VDIOCD0
BCK
LRCK
PCMD
VDIOCD1
PF4/XRDE
PI3/BCKO
P12/LRCKO
PI0/PCMDO
O
SS
EL
XIN
X
TA
L
EXTAL
A
V
SO
SC
A
VS
PLL
A
VD
PLL
D
VS
S3
D
VD
D1
KR
B
K
DI
K
DO
VD
IO
1
KCS
KC
LK
A
VD
M
O
VD
IO
2
TES
T3
T
EST
2
TES
T1
D
V
D
D
3
D
VS
S
1
TES
T0
TCK
T
DI
V
D
IO
3
TM
S
TD
O
NTR
ST
NRST
PF0
PF1
PF2
PF3
PC0
VDIOCD2
PC1
PC2
PC3
DVDD2
DVSS2
PE0
PE1
PE2
PE3
TACK(TES
T6
)
XO
U
T(TES
T5)
TR
ST(T
EST4)
(2/7)
∗
CSP(Chip Size Package)
SUB SYSTEM
CONTROLLER
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
XWE
XRST
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
R/XB
A16
XBYTE
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
XOE
VSS
XCE
A0
∗
CSP(Chip Size Package)
FLASH MEMORY
(NOT SUPPLIED)
(Page 24)
(Page 30)
(Page 27)
Note: When IC1101 on the MAIN board is damaged, exchange
the new MAIN board for the MAIN board which IC damaged.
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