Read Sony NW-E205 / NW-E207 Service Manual online
15
15
NW-E205/E207
NW-E205/E207
SECTION 4
DIAGRAMS
Note on Schematic Diagram:
• All capacitors are in
• All capacitors are in
µ
F unless otherwise noted. (p: pF) 50 WV
or less are not indicated except for electrolytics and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise speci-
fied.
•
%
: indicates tolerance.
•
C
: panel designation.
•
: B+ Line.
• Voltages and waveforms are dc with respect to ground under
no-signal (detuned) conditions.
no mark : POWEN ON
no mark : POWEN ON
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal production toler-
ances.
ances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production toler-
ances.
ances.
• Circled numbers refer to waveforms.
• Signal path.
E
: PLAY BACK
a
: DIGITAL OUT
k
: DIGITAL IN
Note on Printed Wiring Board
•
•
X
: parts extracted from the component side.
•
Y
: parts extracted from the conductor side.
•
: Pattern from the side which enables seeing.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Side A)
Pattern face side: Parts on the pattern face side seen from
(Side A)
the pattern face are indicated.
Parts face side:
Parts on the parts face side seen from
(Side B)
the parts face are indicated.
• MAIN board is multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in the diagram.
cluded in the diagram.
• Lead Layouts
•
Waveforms
– MAIN Board –
1
IC400
<zcm
(XTAL)
44.5 ns
1.4 Vp-p
500 mV/DIV, 20 ns/DIV
2
IC400
<zvz
(TX)
62.4
n
s
1 V/DIV, 40 ns/DIV
3.5 Vp-p
3
IC401
8
(OSCOUT)
30.5
µ
s
500 mV/DIV, 20
µ
s/DIV
1.2 Vp-p
Lead layout of
conventional IC
CSP (chip size package)
surface
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